- 您现在的位置：买卖IC网 > PDF目录378649 > lCL71C03ACPl (Intersil Corporation) Precision 4 1/2 Digit, A/D Converter PDF资料下载
参数资料
| 型号： | lCL71C03ACPl |
| 厂商： | Intersil Corporation |
| 英文描述： | Precision 4 1/2 Digit, A/D Converter |
| 中文描述： | 精密4 1 / 2位，A / D转换 |
| 文件页数： | 6/19页 |
| 文件大小： | 168K |
| 代理商： | LCL71C03ACPL |
3-39
Detailed Description
ANALOG SECTION
Figure 2 shows the equivalent Circuit of the Analog Section
of both the ICL71C03/8052 and the ICL71C03/8068 in the 3
different phases of operation. IF the RUN/HOLD pin is left
open or tied to V+, the system will perform conversions at a
rate determined by the clock frequency: 40,0002 at 4
1
/
2
digit
and 4002 at 3
1
/
2
digit clock periods per cycle (see Figure 3
for details of conversion timing).
Auto-zero Phase I
(Figure 2A)
During the Auto-Zero, the input of the buffer is connected to
V
REF
through switch 2, and switch 3 closes a loop around
the integrator and comparator, the purpose of which is to
charge the auto-zero capacitor until the integrator output
does not change with time. Also, switches 1 and 2 recharge
the reference capacitor to V
REF
.
Input Integrate Phase II
(Figure 2B)
During Input Integrate the auto-zero loop is opened and the
ANALOG INPUT is connected to the BUFFER INPUT
through switch 4 and C
REF
. If the input signal is zero, the
buffer, integrator and comparator will see the same voltage
that existed in the previous state (Auto-Zero). Thus, the
integrator output will not change but will remain stationary
during the entire Input Integrate cycle. If V
IN
is not equal to
zero, and unbalanced condition exists compared to the Auto
Zero phase, and the integrator will generate a ramp whose
slope is proportional to V
IN
. At the end of this phase, the
sign of the ramp is latched into the polarity F/F.
Deintegrate Phase II
(Figures 2C and 2D)
During the Deintegrate phase, the switch drive logic uses the
output of the polarity F/F in determining whether to close
switch 6 or 5. If the input signal is positive, switch 6 is closed
and a voltage which is V
REF
more negative than during
Auto-Zero is impressed on the BUFFER INPUT. Negative
Inputs will cause +2(V
REF
) to be applied to the BUFFER
INPUT via switch 5. Thus, the reference capacitor generates
the equivalent of a (+) or (-) reference from the single
reference voltage with negligible error. The reference voltage
returns the output of the integrator to the zero-crossing point
established in Phase I. The time, or number of counts,
required to do this is proportional to the input voltage. Since
the Deintegrate phase can be twice as long as the Input
Integrate Phase, the input voltage required to give a full
scale reading is 2V
REF
.
System Electrical Specifications: ICL8052/ICL71C03
V++ = +15V, V+ = +5V, V- = -15V, T
A
= 25
o
C, f
CLK
Set for 3 Reading/Sec.
PARAMETER
TEST
CONDITIONS
ICL8068A/ICL71C03
(NOTE 9)
ICL8068A/ICL71C03
(NOTE 10)
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
Zero Input Reading
V
IN
= 0V,
Full Scale = 2V
-0.000
±
0.000
+0.000
-0.000
±
0.000
0.000
Digital
Reading
Ratiometric Error (Note 11)
V
IN
= V
REF
Full Scale = 2V
0.999
1.000
1.001
0.9999
1.0000
1.0001
Digital
Reading
Linearity Over
±
Full Scale (Error of
Reading from Best Straight Line)
-2V
≤
V
IN
≤
+2V
-
0.2
1
-
0.5
1
Counts
Differential Linearity (Difference
between Worst Case Step of Adjacent
Counts and Ideal Step)
-2V
≤
V
IN
≤
+2V
-
0.01
-
-
0.01
-
Counts
Rollover Error (Difference in Reading
for Equal Positive & Negative Voltage
Near Full Scale)
-V
IN
+V
IN
≈
2V
-
0.2
1
-
0.5
1
Counts
Noise (Peak-To-Peak Value Not
Exceeded 95% of Time)
V
IN
= 0V,
Full Scale = 200mV,
Full Scale = 2V
-
20
50
-
-
-
-
30
-
-
μ
V
Leakage Current at Input
V
IN
= 0V
V
IN
= 0V,
0
o
C To 70
o
C
-
5
30
-
3
10
pA
Zero Reading Drift
-
1
5
-
0.5
2
μ
V/
o
C
Scale Factor Temperature Coefficient
V
IN
= 2V,
0
o
C To 70
o
C,
Ext. Ref. 0ppm/
o
C
-
3
15
-
2
5
ppm/
o
C
NOTES:
9. Tested in 3
1
/
2
digit (2,000 count) circuit shown in Figure 5, clock frequency 12kHz. Pin 2 71C03 connected to GND.
10. Tested in 4
1
/
2
digit (20,000 count) circuit shown in Figure 5, clock frequency 120kHz. Pin 2 71C03A open.
11. Tested with a low dielectric absorption integrating capacitor. See Component Selection Section.
12. The temperature range can be extended to 70
o
C and beyond if the Auto-Zero and Reference capacitors are increased to absorb the high
temperature leakage of the 8068.
ICL8052/ICL71C03, ICL8068/ICL71C03
相关PDF资料 |
PDF描述 |
|---|---|
| lCL8052ACPD | Precision 4 1/2 Digit, A/D Converter |
| lCL8052CDD | Precision 4 1/2 Digit, A/D Converter |
| LDA101 | Solid State Current Sensors |
| LDA101S | Solid State Current Sensors |
| LDA101STR | Solid State Current Sensors |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LCL8052ACPD | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Precision 4 1/2 Digit, A/D Converter |
| LCL8052CDD | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Precision 4 1/2 Digit, A/D Converter |
| LCL8068ACJD | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Precision 4 1/2 Digit, A/D Converter |
| LC-LA1233P | 功能描述:密封铅酸电池 12V 33AH BOLT/NUT RoHS:否 制造商:CSB 输出电压:12 V 容量: 大小: 端接类型:Faston Tab |
| LC-LA1233PG | 制造商:Panasonic Industrial Devices 功能描述: |
发布紧急采购，3分钟左右您将得到回复。