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参数资料
型号： LCMXO1200C-3TN100I
厂商： Lattice Semiconductor Corporation
文件页数： 15/88页
文件大小： 0K
描述： IC PLD 1200LUTS 73I/O 100-TQFP
标准包装： 90
系列： MachXO
可编程类型： 系统内可编程
最大延迟时间 tpd(1)： 5.1ns
电压电源 - 内部： 1.71 V ~ 3.465 V
宏单元数： 600
输入/输出数： 73
工作温度： -40°C ~ 100°C
安装类型： 表面贴装
封装/外壳： 100-LQFP
供应商设备封装： 100-TQFP（14x14）
包装： 托盘
其它名称： 220-1378
LCMXO1200C-3TN100I-ND
Architecture
MachXO Family Data Sheet
The EBR memory supports three forms of write behavior for single or dual port operation:
1. Normal – data on the output appears only during the read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
2. Write Through – a copy of the input data appears at the output of the same port. This mode is supported for
all data widths.
3. Read-Before-Write – when new data is being written, the old contents of the address appears at the output.
This mode is supported for x9, x18 and x36 data widths.
FIFO Configuration
The FIFO has a write port with Data-in, CEW, WE and CLKW signals. There is a separate read port with Data-out,
RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The
Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR.
The range of programming values for these flags are in Table 2-7.
Table 2-7. Programmable FIFO Flag Ranges
Flag Name
Full (FF)
Almost Full (AF)
Almost Empty (AE)
Empty (EF)
Programming Range
1 to (up to 2 N -1)
1 to Full-1
1 to Full-1
0
N = Address bit width
The FIFO state machine supports two types of reset signals: RSTA and RSTB. The RSTA signal is a global reset
that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset
state. The RSTB signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in
the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from the
FIFO.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respec-
tively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both
ports are as shown in Figure 2-13.
2-12
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相关代理商/技术参数
参数描述
LCMXO1200C-3TN144C 功能描述:CPLD - 复杂可编程逻辑器件 1200 LUTS 113 I/O RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LCMXO1200C-3TN144I 功能描述:CPLD - 复杂可编程逻辑器件 1200 LUTs 113 IO 1.8 /2.5/3.3V -3 Spd I RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LCMXO1200C-4B256C 功能描述:CPLD - 复杂可编程逻辑器件 1200 LUTs 211 I/O 1.8/2.5/3.3V -4 SPD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LCMXO1200C-4B256I 功能描述:CPLD - 复杂可编程逻辑器件 1200 LUTs 211 I/O 1.8/2.5/3.3V -4 SPD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LCMXO1200C-4BN256C 功能描述:CPLD - 复杂可编程逻辑器件 1200 LUTs 211 I/O 1.8/2.5/3.3V -4 SPD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
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