参数资料
型号: LCMXO1200E-5TN100C
厂商: Lattice Semiconductor Corporation
文件页数: 33/88页
文件大小: 0K
描述: IC FPGA 1.2KLUTS 100TQFP
标准包装: 90
系列: MachXO
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 3.6ns
电压电源 - 内部: 1.14 V ~ 1.26 V
宏单元数: 600
输入/输出数: 73
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
DC and Switching Characteristics
MachXO Family Data Sheet
Table 3-1. LVDS DC Conditions
Over Recommended Operating Conditions
Z OUT
R S
R P
R T
V OH
V OL
V OD
V CM
Z BACK
I DC
Parameter
Description
Output impedance
Driver series resistor
Driver parallel resistor
Receiver termination
Output high voltage
Output low voltage
Output differential voltage
Output common mode voltage
Back impedance
DC output current
Typical
20
294
121
100
1.43
1.07
0.35
1.25
100
3.66
Units
?
?
?
?
V
V
V
V
?
mA
BLVDS
The MachXO family supports the BLVDS standard through emulation. The output is emulated using complemen-
tary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. The input standard
is supported by the LVDS differential input buffer on certain devices. BLVDS is intended for use when multi-drop
and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible
solution for bi-directional multi-point differential signals.
Figure 3-2. BLVDS Multi-point Output Example
Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential
2.5V
2.5V
16mA
2.5V
16mA
80
80
45-90 ohms
45-90 ohms
80
16mA
2.5V
16mA
+
80
80
.. .
80
80
+
-
-
2.5V
16mA
2.5V
16mA
-
2.5V
16mA
2.5V
16mA
-
3-7
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