参数资料
型号: LCMXO640C-5T144C
厂商: Lattice Semiconductor Corporation
文件页数: 10/88页
文件大小: 0K
描述: IC PLD 640LUTS 113I/O 144-TQFP
标准包装: 60
系列: MachXO
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 3.5ns
电压电源 - 内部: 1.71 V ~ 3.465 V
宏单元数: 320
输入/输出数: 113
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 144-LQFP
供应商设备封装: 144-TQFP(20x20)
包装: 托盘
Architecture
MachXO Family Data Sheet
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
Clock/Control Distribution Network
The MachXO family of devices provides global signals that are available to all PFUs. These signals consist of four
primary clocks and four secondary clocks. Primary clock signals are generated from four 16:1 muxes as shown in
Figure 2-7 and Figure 2-8. The available clock sources for the MachXO256 and MachXO640 devices are four dual
function clock pins and 12 internal routing signals. The available clock sources for the MachXO1200 and
MachXO2280 devices are four dual function clock pins, up to nine internal routing signals and up to six PLL out-
puts.
Figure 2-7. Primary Clocks for MachXO256 and MachXO640 Devices
12
4
16:1
16:1
16:1
16:1
Primary Clock 0
Primary Clock 1
Primary Clock 2
Primary Clock 3
Routing
Clock
Pads
2-7
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相关代理商/技术参数
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LCMXO640C-5TN144C4W 制造商:Lattice Semiconductor Corporation 功能描述:MACHXO PLD FLASH SCRAM 1.8V 640
LCMXO640C-L-EV 功能描述:可编程逻辑 IC 开发工具 MachXO 640 Eval Brd Standard RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: