参数资料
型号: LCMXO640C-5T144C
厂商: Lattice Semiconductor Corporation
文件页数: 9/88页
文件大小: 0K
描述: IC PLD 640LUTS 113I/O 144-TQFP
标准包装: 60
系列: MachXO
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 3.5ns
电压电源 - 内部: 1.71 V ~ 3.465 V
宏单元数: 320
输入/输出数: 113
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 144-LQFP
供应商设备封装: 144-TQFP(20x20)
包装: 托盘
Architecture
MachXO Family Data Sheet
Figure 2-6. Distributed Memory Primitives
AD0
SPR16x2
DPR16x2
AD1
WAD0
RAD0
AD2
AD3
DI0
DI1
WRE
CK
DO0
DO1
WAD1
WAD2
WAD3
DI0
DI1
WCK
WRE
RAD1
RAD2
RAD3
RDO0
RDO1
WDO0
WDO1
ROM16x1
AD0
AD1
AD2
DO0
AD3
ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is
accomplished through the programming interface during configuration.
PFU Modes of Operation
Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the
functionality possible at the PFU level.
Table 2-4. PFU Modes of Operation
Logic
LUT 4x8 or
MUX 2x1 x 8
LUT 5x4 or
MUX 4x1 x 4
LUT 6x 2 or
MUX 8x1 x 2
LUT 7x1 or
MUX 16x1 x 1
Ripple
2-bit Add x 4
2-bit Sub x 4
2-bit Counter x 4
2-bit Comp x 4
RAM
SPR16x2 x 4
DPR16x2 x 2
SPR16x4 x 2
DPR16x4 x 1
SPR16x8 x 1
ROM
ROM16x1 x 8
ROM16x2 x 4
ROM16x4 x 2
ROM16x8 x 1
Routing
There are many resources provided in the MachXO devices to route signals individually or as buses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-
ments.
The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2
(spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connec-
tions in the horizontal and vertical directions.
2-6
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