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| 型号： | LCMXO640E-3T100C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 44/88页 |
| 文件大小： | 0K |
| 描述： | IC PLD 640LUTS 74I/O 100-TQFP |
| 标准包装： | 90 |
| 系列： | MachXO |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 4.9ns |
| 电压电源 - 内部： | 1.14 V ~ 1.26 V |
| 宏单元数： | 320 |
| 输入/输出数： | 74 |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
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MachXO Family Data Sheet
Pinout Information
November 2012
Signal Descriptions
Data Sheet DS1002
Signal Name
I/O
Descriptions
General Purpose
[Edge] indicates the edge of the device on which the pad is located. Valid edge designa-
tions are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on which the
PIO Group exists. When Edge is T (Top) or (Bottom), only need to specify Row Number.
When Edge is L (Left) or R (Right), only need to specify Column Number.
[A/B/C/D] indicates the PIO within the group to which the pad is connected.
P[Edge] [Row/Column
Number]_[A/B/C/D]
I/O Some of these user-programmable pins are shared with special function pins. When not
used as special function pins, these pins can be programmed as I/Os for user logic.
During configuration of the user-programmable I/Os, the user has an option to tri-state the ?
I/Os and enable an internal pull-up, pull-down or buskeeper resistor. This option also
applies to unused pins (or those not bonded to a package pin). The default during configu-
ration is for user-programmable I/Os to be tri-stated with an internal pull-down resistor
enabled. When the device is erased, I/Os will be tri-stated with an internal pull-down resis-
tor enabled. Some pins, such as PROGRAMN and JTAG pins, default to tri-stated I/Os with
pull-up resistors enabled when the device is erased.
NC
GND
VCC
VCCIOx
—
—
—
—
No connect.
GND – Ground. Dedicated pins. It is recommended that all GNDs are tied together.
V CC – The power supply pins for core logic. Dedicated pins. It is recommended that all
VCCs are tied to the same supply.
VCCIO – The power supply pins for I/O Bank x. Dedicated pins. It is recommended that all
VCCIOs located in the same bank are tied to the same supply.
PLL and Clock Functions (Used as user-programmable I/O pins when not used for PLL or clock pins)
[LOC]_GPLL[T, C]_IN
[LOC]_GPLL[T, C]_FB
PCLK [n]_[2:0]
—
—
—
Reference Clock (PLL) input pads: [LOC] indicates location. Valid designations are L (Left
PLL) and R (Right PLL). T = true and C = complement.
Optional Feedback (PLL) input pads: [LOC] indicates location. Valid designations are L
(Left PLL) and R (Right PLL). T = true and C = complement.
Primary Clock pads. One to three clock pads per side.
Test and Programming (Dual function pins used for test access port and during sysCONFIG?)
TMS
TCK
TDI
TDO
JTAGENB
I
I
I
O
I
Test Mode Select input pin, used to control the 1149.1 state machine.
Test Clock input pin, used to clock the 1149.1 state machine.
Test Data input pin, used to load data into the device using an 1149.1 state machine.
Output pin – Test Data output pin used to shift data out of the device using 1149.1.
Optionally controls behavior of TDI, TDO, TMS, TCK. If the device is configured to use the
JTAG pins (TDI, TDO, TMS, TCK) as general purpose I/O, then:
If JTAGENB is low: TDI, TDO, TMS and TCK can function a general purpose I/O.
If JTAGENB is high: TDI, TDO, TMS and TCK function as JTAG pins.
For more details, refer to TN1204, MachXO2 Programming and Configuration Usage
Configuration (Dual function pins used during sysCONFIG)
PROGRAMN
INITN
I
I/O
Initiates configuration sequence when asserted low. This pin always has an active pull-up.
Open Drain pin. Indicates the FPGA is ready to be configured. During configuration, a pull-
up is enabled.
? 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
4-1
DS1002 Pinouts_01.9
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相关代理商/技术参数 |
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|---|---|
| LCMXO640E-3T100I | 功能描述:CPLD - 复杂可编程逻辑器件 640 LUTs 74 IO 1.2V -3 Spd I RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LCMXO640E-3T144C | 功能描述:CPLD - 复杂可编程逻辑器件 640 LUTs 113 IO 1.2V -3 Spd RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LCMXO640E-3T144I | 功能描述:CPLD - 复杂可编程逻辑器件 640 LUTs 113 IO 1.2V -3 Spd I RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LCMXO640E-3TN100C | 功能描述:CPLD - 复杂可编程逻辑器件 640 LUTs 74 IO 1.2V -3 Spd RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LCMXO640E-3TN100I | 功能描述:CPLD - 复杂可编程逻辑器件 640 LUTs 74 IO 1.2V -3 Spd I RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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