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参数资料
| 型号： | LF3310 |
| 厂商： | Logic Devices Incorporated |
| 英文描述： | Horizontal / Vertical Digital Image Filter |
| 中文描述： | 水平/垂直数字图像滤波器 |
| 文件页数： | 15/21页 |
| 文件大小： | 287K |
| 代理商： | LF3310 |
DEVICES INCORPORATED
Video Imaging Products
15
LF3310
Horizontal / Vertical Digital Image Filter
11/08/2001-LDS.3310-H
all four data values are loaded.
After the last data value is loaded, the
interface will expect a new address
value on the next clock cycle. After
the next address value is loaded, data
loading will begin again as previously
discussed. As long as data is loaded
into the interface, HLD must remain
LOW. After all desired coefficient
banks and Configuration/ Control
Registers are loaded with data, the LF
Interface
TM
must be disabled. This is
It takes 9S clock cycles to load S
coefficient sets into the device.
Therefore, it takes 2304 clock cycles to
load all 256 coefficient sets. Assuming
an 83 MHz clock rate, all 256 coeffi-
cient sets can be updated in 28.8 μs,
which is well within vertical blanking
time. It takes 5S or 3S clock cycles to
load S round or limit registers respec-
tively. Therefore, it takes 256 clock
cycles to update all round and limit
registers (both horizontal and verti-
cal). Assuming an 83 MHz clock rate,
T
ABLE
16.
C
ONFIGURATION
R
EGISTER
L
OADING
F
ORMAT
H/VCF
11
H/VCF
10
H/VCF
9
H/VCF
8
H/VCF
7
H/VCF
6
H/VCF
5
H/VCF
4
H/VCF
3
H/VCF
2
H/VCF
1
H/VCF
0
1st Word - Address
0
0
1
0
0
0
0
0
0
1
0
0
2nd Word - Data
0
0
0
0
0
0
0
0
0
0
1
1
T
ABLE
17.
R
OUND
R
EGISTER
L
OADING
F
ORMAT
H/VCF
11
H/VCF
10
H/VCF
9
H/VCF
8
H/VCF
7
H/VCF
6
H/VCF
5
H/VCF
4
H/VCF
3
H/VCF
2
H/VCF
1
H/VCF
0
1st Word - Address
1
0
0
0
0
0
0
0
1
1
0
0
2nd Word- Data
R
R
R
R
1
0
1
0
0
0
1
0*
3rd Word - Data
R
R
R
R
1
1
1
1
0
1
0
0
4th Word - Data
R
R
R
R
1
0
0
0
0
0
1
1
5th Word - Data
R
R
R
R
0**
1
1
1
0
1
1
0
R = Reserved. Must be set to “0”.
* This bit represents the LSB of the Round Register.
** This bit represents the MSB of the Round Register.
all horizontal and vertical Round/
Limit registers can be updated in
3.08 μs.
The coefficient banks and Configura-
tion/ Control Registers are not loaded
with data until all data values for the
specified address are loaded into the
LF Interface
TM
. In other words, the
coefficient banks are not written to
until all eight coefficients have been
loaded into the LF Interface
TM
. A
round register is not written to until
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LF3310QC12 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:Horizontal / Vertical Digital Image Filter |
| LF3310QC15 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:Horizontal / Vertical Digital Image Filter |
| LF3310QC18 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Digital Filter |
| LF3310QC25 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Digital Filter |
| LF3311 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:Horizontal / Vertical Digital Image Filter |
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