LFEC6E-5TN144C (Lattice) PDF资料下载 Datasheet(89/163 页)

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参数资料

型号：	LFEC6E-5TN144C
厂商：	Lattice Semiconductor Corporation
文件页数：	89/163页
文件大小：	0K
描述：	IC FPGA 6.1KLUTS 97I/O 144-TQFP
标准包装：	60
系列：	EC
逻辑元件/单元数：	6100
RAM 位总计：	94208
输入/输出数：	97
电源电压：	1.14 V ~ 1.26 V
安装类型：	表面贴装
工作温度：	0°C ~ 85°C
封装/外壳：	144-LQFP
供应商设备封装：	144-TQFP（20x20）

2-28

Architecture

LatticeECP/EC Family Data Sheet

Polarity Control Logic

In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the

internal system Clock (during the READ cycle) is unknown.

The LatticeECP/EC family contains dedicated circuits to transfer data between these domains. To prevent setup

and hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is

used. This changes the edge on which the data is registered in the synchronizing registers in the input register

block. This requires evaluation at the start of each READ cycle for the correct clock polarity.

Prior to the READ operation in DDR memories DQS is in tristate (pulled by termination). The DDR memory device

drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to

control the polarity of the clock to the synchronizing registers.

sysI/O Buffer

Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the

periphery of the device in eight groups referred to as Banks. The sysI/O buffers allow users to implement the wide

variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.

sysI/O Buffer Banks

LatticeECP/EC devices have eight sysI/O buffer banks; each is capable of supporting multiple I/O standards. Each

sysI/O bank has its own I/O supply voltage (VCCIO), and two voltage references VREF1 and VREF2 resources allow-

ing each bank to be completely independent from each other. Figure 2-34 shows the eight banks and their associ-

ated supplies.

In the LatticeECP/EC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI and PCI-

X) are powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold

input independent of VCCIO. In addition to the bank VCCIO supplies, the LatticeECP/EC devices have a VCC core logic

power supply, and a VCCAUX supply that power all differential and referenced buffers.

Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer-

enced input buffers. In the LatticeECP/EC devices, some dedicated I/O pins in a bank can be configured to be a

reference voltage supply pin. Each I/O is individually configurable based on the bank’s supply and reference volt-

ages.

相关代理商/技术参数	参数描述
LFEC6E-5TN144I	制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC6E-L-EV	功能描述:可编程逻辑 IC 开发工具 Eval Board for EC6 RoHS:否制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:
LFECP10	制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFECP10E-3F256C	功能描述:FPGA - 现场可编程门阵列 10.2K LUTs RoHS:否制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFECP10E-3F256I	功能描述:FPGA - 现场可编程门阵列 10.2K LUTs 195 I/O RoHS:否制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256

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