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参数资料
| 型号： | LFX200EB-05FN256C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 26/119页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 210KGATES 256FPBGA |
| 标准包装： | 90 |
| 系列： | ispXPGA® |
| 逻辑元件/单元数： | 2704 |
| RAM 位总计： | 113664 |
| 输入/输出数： | 160 |
| 门数： | 210000 |
| 电源电压： | 2.3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 256-BGA |
| 供应商设备封装： | 256-FPBGA（17x17） |
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Lattice Semiconductor
ispXPGA Family Data Sheet
10
Figure 10. ispXPGA PIC
Programmable Input/Output
The PIO is the building block of a PIC. The PIO has a total of 11 inputs and five outputs. Nine of the 11 inputs are
generated from routing. The inputs from routing are the PIO Input (IN), Feed-Thru (FT), Clock (CLK), Input Clock
Enable (ICE), Input Set/Reset (ISR), Output Clock Enable (OCEN), Output Set/Reset (OSR), PIO Output Enable
(OEN), and PIO Input Enable (IEN). The remaining inputs are the sysIO input buffer signal and the Global Set/
Reset signal. Three of the five outputs (OUT0, OUT1, and OE) feed routing. The last two outputs feed the sysIO
buffer directly as the output and output enable of the sysIO output buffer.
PIOs associated with sysHSI blocks contain two additional inputs and outputs to support the sysHSI block. The two
inputs come from the sysHSI block associated with the PIO, and the two outputs feed the sysHSI block. One of the
inputs routes directly through the PIO to routing, while the other is multiplexed with the Feed-Thru, register bypass,
and Q output of the register to form the OUT1 output of the PIO. The outputs to the sysHSI block are the same sig-
nals as the outputs which feed the sysIO buffers (sysIO Output and sysIO Output Enable).
Each PIO has an input register, an output register, and an output enable register as shown in Figure 11. The input
register path of the PIO has a ‘delay’ option, which slows the data-flow. A two-input OR function of the Global Set/
Reset (GSR) and Set/Reset (ISR or OSR) signals creates the set/reset term for the respective registers. Each PIO
has two pairs of set/reset and clock enable signals. One is exclusive to the input register, whereas the other is com-
mon for both the output and output enable registers. The clock (CLK) is common to all registers in a PIO, and the
polarity of the clock is controllable. The input, output, and the output enable registers can be configured as a latch
or D-type flip-flop. Each PIO is capable of generating an output enable signal, which in turn becomes a PIC output.
PIC
PIO0
PIO1
OE1 OE0
sysIO
9
2
To routing
Only for PICs
associated with
sysHSI blocks
Only for PICs
associated with
sysHSI blocks
To routing
From routing
GSR
sysIO
From sysHSI block
To sysHSI block
2
9
From sysHSI block
To sysHSI block
2
SELECT
DEVICES
DISCONTINUED
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LFX200EB-05FN516C | 功能描述:FPGA - 现场可编程门阵列 E-Ser210K Gt ispJTA G 2.5/3.3V -5 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| LFX200EB-3F256C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:ispXPGA Family |
| LFX200EB-3F256I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:ispXPGA Family |
| LFX200EB-3F516C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:ispXPGA Family |
| LFX200EB-3F516I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:ispXPGA Family |
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