
LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
10-4
Figure 10-4. DQ-DQS Grouping
Figure 10-4 shows a typical DQ-DQS group for both the LatticeECP/EC device and the LatticeXP device. The ninth
I/O of this group of 16 I/Os (for LatticeECP/EC) or 14 I/Os (for LatticeXP) is the dedicated DQS pin. All eight pads
before the DQS and seven (for LatticeECP/EC) or four (for LatticeXP) pads after the DQS are covered by this DQS
bus span. The user can assign any eight of these I/O pads to be DQ data pins. Hence, to implement a 32-bit wide
memory interface you would need to use four such DQ-DQS groups.
When not interfacing with the memory, the dedicated DQS pin can be used as a general purpose I/O. Each of the
dedicated DQS pin is internally connected to the DQS phase shift circuitry. The pinout information contained in the
LatticeECP/EC and LatticeXP device data sheets shows pin locations for the DQS pads.
Table 10-2 shows an
extract from the LatticeECP/EC data sheet. In this case, the DQS is marked as LDQS6 (L=left side, 6 =associated
PFU row/column). Since DQS is always the fifth true pad in the DQ-DQS group, counting from low to high PFU
row/column number, LDQS6 will cover PL2A to PL9B. Following this convention, there are eight pads before and
seven pads after DQS for DQ available following counter-clockwise for the left and bottom sides of the device, and
following clockwise for the top and right sides of the device. The user can assign any eight of these pads to be DQ
data signals. The LatticeXP device follows the same method.
Table 10-3. EC20 Pinout (from LatticeECP/EC Family Data Sheet)
Ball Function
Bank
LVDS
Dual Function
484 fpBGA
672 fpBGA
PL2A
7
T
VREF2_7
D4
E3
PL2B
7
C
VREF1_7
E4
PL3A
7
T
—
C3
B1
PL3B
7
C
—
B2
C1
PL4A
7
T
—
E5
F3
PL4B
7
C
—
F5
G3
PL5A
7
T
—
D3
D2
PL5B
7
C
—
C2
E2
PL6A
7
T
LDQS6
F4
D1
PL6B
7
C
—
G4
E1
PL7A
7
T
—
E3
F2
PL7B
7
C
—
D2
G2
PL8A
7
T
LUM0_PLLT_IN_A
B1
F6
PL8B
7
C
LUM0_PLLC_IN_A
C1
G6
PL9A
7
T
LUM0_PLLT_FB_A
F3
H4
PL9B
7
C
LUM0_PLLC_FB_A
E2
G4
PL11A
7
T
—
G5
J4
DQS PAD
n* I/O PADS
(Ninth I/O Pad)
DQ, DM or VREF1
*For LatticeECP/EC: n = 16, for LatticeXP: n = 14.