
13-2
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
Figure 13-1. Programming Block Diagram
Configuration Pins
The LatticeXP supports two types of sysCONFIG pins, dedicated and dual-purpose. The dual-purpose pins are
available as extra I/O pins if they are not used for configuration.
Two configuration mode pins, along with a programmable option, control the dual-purpose configuration pins. The
configuration mode pins (CFG) are generally hard wired on the PCB and determine which configuration mode will
be used; the programmable option is accessed via preferences in Lattice ispLEVER
design software, or as HDL
source file attributes, and allows the user to protect the configuration pins from accidental use by the user or the
place-and-route software. The LatticeXP devices also support ispJTAG for configuration, including transparent
readback, and for JTAG testing. The following sections describe the functionality of the sysCONFIG and JTAG pins.
Note that JTAG and ispJTAG will be used interchangeably in this document.
Table 13-1 is provided for reference.
Table 13-1. Configuration Pins for the LatticeXP Device
Pin Name
I/O Type
Pin Type
Mode Used
CFG[1:0]
Input, weak pull-up
Dedicated
All
PROGRAMN
Input, weak pull-up
Dedicated
All
INITN
Bi-Directional Open Drain, weak pull-up
Dedicated
All
DONE
Bi-Directional Open Drain with weak pull-up or Active Drive
Dedicated
All
CCLK
Input or Output
Dedicated
All
DIN
Input, weak pull-up
Dual-Purpose
Serial
DOUT/CSON
Output
Dual-Purpose
Serial or Parallel
CSN
Input, weak pull-up
Dual-Purpose
Parallel
CS1N
Input, weak pull-up
Dual-Purpose
Parallel
WRITEN
Input, weak pull-up
Dual-Purpose
Parallel
BUSY
Output, tri-state, weak pull-up
Dual-Purpose
Parallel
D[0:7]
Input or Output
Dual-Purpose
Parallel
TDI
Input, weak pull-up
JTAG
ispJTAG 1149.1 TAP
sysCONFIG Port
Flash Memory
Space
JTAG 1532
Master/Slave Serial
Slave Parallel
SRAM Memory
Space
Port
Mode
Memory Space
Program in seconds
(Slave Parallel Only)
Program in
milliseconds
Program in
microseconds
SDM
,