参数资料
型号: LIS3L02DQ
厂商: STMICROELECTRONICS
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, QCC44
封装: 7 X 7 MM, 1.80 MM HEIGHT, QFN-44
文件页数: 2/20页
文件大小: 473K
代理商: LIS3L02DQ
Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
- Obsolete
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LIS3L02DQ
10/20
6.3 SPI Bus Interface
The SPI interface present inside the LIS3L02DQ is a bus slave. The SPI allows to write and read the reg-
isters of the device. The Serial Interface interacts with the outer world with 4 wires: CS, SPC, SDI and
SDO.The maximum frequency is related to the Vdd_IO supply voltage.In particular in the 2.4 V - 3.6 V
range is 8 MHz while under 2.4 V is 4 MHz.
6.3.1 Read & Write registers
Figure 5. Read & write protocol
CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of the transmis-
sion and goes back high at the end. SPC is the Serial Port Clock and it is controlled by the SPI master. It
is stopped high when CS is high (no transmission). SDI and SDO are respectively the Serial Port Data
Input and Output. Those lines are driven at the falling edge of SPC and should be captured at the rising
edge of SPC.
Both the Read Register and Write Register commands are completed in 16 clock pulses. Bit duration is
the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after
the falling edge of CS while the last bit (bit 15) starts at the last falling edge of SPC just before the rising
edge of CS.
– bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the
device is read. In latter case, the chip will drive SDO at the start of bit 8.
– bit 1-7: address AD(6:0). This is the address field of the indexed register.
– bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSB first).
– bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSB first).
6.3.2 SPI Read
Figure 6. SPI Read protocol
The SPI Read command consists of 16 clock pulses:
– bit 0: READ bit. The value is 1.
CS
SPC
SPDI
SPDO
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7DI6
DI5DI4
DI3DI2
DI1
DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS
SPC
SDI
SPDO
RW
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
AD6 AD5 AD4 AD3 AD2 AD1 AD0
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