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参数资料
| 型号： | LLV5256GP |
| 元件分类： | 稳压器 |
| 英文描述： | 0.6 A SWITCHING REGULATOR, 1200 kHz SWITCHING FREQ-MAX, QCC20 |
| 封装： | 3 X 3 MM, VCT-20 |
| 文件页数： | 5/9页 |
| 文件大小： | 142K |
| 代理商： | LLV5256GP |
LV5256GP
No.A1277-5/9
Block Diagrams and Sample Application Circuit 1 (Step-down)
BIAS
VREF
TSD
disable
ot
Vref
(1.0V±1%)
Vref1R2
(1.2V)
VREG
UVLO
3.3V
disable
2.8V/2.5V
uvlo
OSC
0.5V
1.0V
+
du_sel
disable
ot
uvlo
tout
pwm Control
Logic
L/S
+
disable
uvlo
VrefR2
R
SQ
tout
disable
uvlo
+
Vref
+
Vref1R2
disable
L/S
VREG
Vout-5
vdd
pin heap 17 pin
FB
×0.8
×0.4
IN
V1
or
V2
OCP
GND/
OPEN
0.01
F at 1.25ms
DU_SEL
OPC_SEL
GND/OPEN:
×0.8
REG_O:
×0.4
0.033
F at 3.3ms
TRAC_IN
SS
ONOFF
VDD
0.1
F
VDD=2.9 to 3.1V
LGND
SBD
22
H
PGND
SW
4.7
F
VOUT
VOUT-5
1
F
VIN
VIN=4.5 to 10V
REG_O
RT
0.1
F
100k
at 1MHz
0.022
F
du_sel
V1 (Normal operation)
=1.0V to VIN
V2 (Tracking operaton)
=0V to VIN
LDO with OPC
Sample Application Circuit 2 (Step-up)
BIAS
VREF
TSD
disable
ot
Vref
(1.0V±1%)
Vref1R2
(1.2V)
VREG
UVLO
3.3V
disable
2.8V/2.5V
uvlo
OSC
0.5V
1.0V
+
du_sel
disable
ot
uvlo
tout
pwm Control
Logic
L/S
+
disable
uvlo
VrefR2
R
SQ
tout
disable
uvlo
+
Vref
+
Vref1R2
disable
L/S
VREG
Vout-5
vdd
pin heap 17 pin
FB
×0.8
×0.4
IN
VOUT1
or
VOUT2
OCP
REG_O
0.01
F at 1.25ms
DU_SEL
OPC_SEL
GND/OPEN:
×0.8
REG_O:
×0.4
0.033
F at 3.3ms
TRAC_IN
SS
ONOFF
VDD
0.1
F
VDD=2.9~3.1V
LGND
10
H
PGND
SW
VOUT
VOUT-5
1
F
VIN
VIN=4.5~10V
REG_O
RT
0.1
F
100k
at 1MHz
0.022
F
4.7
F
du_sel
VOUT1 (Normal operation)
=5.3V to 14V
VOUT2 (Tracking operaton)
=VIN or more
LDO with OPC
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