参数资料
型号: LM10506TME
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 电源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PBGA34
封装: 0.40 MM PITCH, MICRO SMD-34
文件页数: 15/34页
文件大小: 1020K
代理商: LM10506TME
19.2 BUCK REGULATORS OPERATION
A buck converter contains a control block, a switching PFET
connected between input and output, a synchronous rectify-
ing NFET connected between the output and ground and a
feedback path. The following figure shows the block diagram
of each of the three buck regulators integrated in the device.
30166208
FIGURE 4. Buck Functional Diagram
During the first portion of each switching cycle, the control
block turns on the internal PFET switch. This allows current
to flow from the input through the inductor to the output filter
capacitor and load. The inductor limits the current to a ramp
with a slope of (V
IN – VOUT)/L by storing energy in a magnetic
field. During the second portion of each cycle, the control
block turns the PFET switch off, blocking current flow from the
input, and then turns the NFET synchronous rectifier on. The
inductor draws current from ground through the NFET to the
output filter capacitor and load, which ramps the inductor cur-
rent down with a slope of (–V
OUT)/L.
The output filter stores charge when the inductor current is
high, and releases it when low, smoothing the voltage across
the load. The output voltage is regulated by modulating the
PFET switch on time to control the average current sent to the
load. The effect is identical to sending a duty-cycle modulated
rectangular wave formed by the switch and synchronous rec-
tifier at the SW pin to a low-pass filter formed by the inductor
and output filter capacitor. The output voltage is equal to the
average voltage at the SW pin.
19.2.1 Buck Regulators Description
The LM10506 incorporates three high-efficiency synchronous
switching buck regulators that deliver various voltages from a
single DC input voltage. They include many advanced fea-
tures to achieve excellent voltage regulation, high efficiency
and fast transient response time. The bucks feature voltage
mode architecture with synchronous rectification.
Each of the switching regulators is specially designed for
high-efficiency operation throughout the load range. With a
2MHz typical switching frequency, the external L- C filter can
be small and still provide very low output voltage ripple. The
bucks are internally compensated to be stable with the rec-
ommended external inductors and capacitors as detailed in
the application diagram. Synchronous rectification yields high
efficiency for low voltage and high output currents.
All bucks can operate up to a 100% duty cycle allowing for the
lowest possible input voltage that still maintains the regulation
of the output. The lowest input to output dropout voltage is
achieved by keeping the PMOS switch on.
Additional features include soft-start, undervoltage lockout,
bypass, and current and thermal overload protection. To re-
duce the input current ripple, the device employs a control
circuit that operates the 3 bucks at 120° phase. These bucks
are nearly identical in performance and mode of operation.
They can operate in FPWM (forced PWM) or automatic mode
(PWM/PFM).
19.2.2 PWM Operation
During PWM operation the converter operates as a voltage-
mode controller with input voltage feed forward. This allows
the converter to achieve excellent load and line regulation.
The DC gain of the power stage is proportional to the input
voltage. To eliminate this dependence, a feed forward voltage
inversely proportional to the input voltage is introduced.
In Forced PWM Mode the bucks always operate in PWM
mode regardless of the output current.
In Automatic Mode, if the output current is less than 70 mA
(typ.), the bucks automatically transition into PFM (Pulse Fre-
quency Modulation) operation to reduce the current con-
sumption. At higher than 100 mA (typ.) they operate in PWM
mode. This increases the efficiency at lower output currents.
The 30 mA (typ.) hysteresis is designed in for stable Mode
transition.
While in PWM mode, the output voltage is regulated by
switching at a constant frequency and then modulating the
energy per cycle to control power to the load. At the beginning
of each clock cycle the PFET switch is turned on, and the
inductor current ramps up until the comparator trips and the
control logic turns off the switch. The current limit comparator
can also turn off the switch in case the current limit of the
PFET is exceeded. In this case the NFET switch is turned on
and the inductor current ramps down. The next cycle is initi-
ated by the clock turning off the NFET and turning on the
PFET.
www.national.com
22
LM10506
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