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参数资料
| 型号： | LM10506TMX-A |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PBGA34 |
| 封装： | 0.40 MM PITCH, MICRO SMD-34 |
| 文件页数： | 19/34页 |
| 文件大小： | 1020K |
| 代理商： | LM10506TMX-A |
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register 0x09. The STANDBY pin is internally pulled down,
and there is a 1 second delay during powerup before the state
of the STANDBY pin is checked. Note: If Buck 1 and Buck 2
are already disabled, and the STANDBY pin is asserted high,
then Buck 3 will not go to PSML – for further instructions, see
Bucks 1 and 2 will be ramped down when the disable signal
is given. Buck 1 starts ramping 2ms after Buck 2 has started
ramping.
Entering Standby Sequence will be:
1.
Buck 3
→ PSML (Programmable Standby Mode Level)
2.
2 msec delay
3.
Buck 2
→ Disabled
4.
2 msec delay
5.
Buck 1
→ Disabled
An internal 22 k
pull down resistor (±30%) is attached to the
FB pin of Buck 1 and Buck 2. Buck 1 and 2 outputs are pulled
to ground level when they are disabled to discharge any
residual charge present in the output circuitry. When STAND-
BY transitions to a low, Buck 1 is again enabled followed by
Buck 2. Buck 3 will go back to its previous state.
When waking up from Standby, the sequence will be:
1.
Buck 3
→ Previous State
2.
2 msec delay
3.
Buck 2 and Buck 3 transition together
→ Previous State
20.4.2 STANDBY Programming via SPI
There is no bit which has the same function as STANDBY
PIN. There is only one requirement programming LM10506
into Standby Mode via SPI. Setting LDO Sleep Mode bit high
must be the last move when entering Standby Mode and pro-
gramming the bit low when waking from Standby Mode must
be the first move. Disabling or programming the Bucks to new
level is the user’s decision based on power consumption and
other requirements.
The following section describes how to program the chip into
Standby Mode corresponding to STANDBY PIN function. To
program the LM10506 to Standby Mode via SPI Buck 1 and
Buck 2 must be disabled by host device (Register 0x0A bit 1
and 0). Buck 3 must be programmed to desired level using
Register 0x00. After Buck 3 has finished ramping LDO Sleep
Mode bit must be set high (Register 0x0E bit 1). To wake
LM10506 from Standby Mode LDO Sleep Mode bit must be
set low (Register 0x0E bit 1). Buck 1 and 2 must be enabled.
Buck 3 voltage must be programmed to previous output level.
20.5 HL_B2, HL_B3 FUNCTION
The HL_B2/3 pins are digital pins which control alternate volt-
age selections of Buck 2 and Buck 3, respectively. HL_B2 has
an internal pulldown which defaults to a 1.8V output voltage
selection for Buck 2. Alternatively, if HL_B2 is driven high, an
output voltage of 3.0V (or 2.0V for LM10506-A) is selected.
HL_B3 has an internal pullup which defaults to a 1.2V output
voltage selection for Buck 3. Alternatively, if HL_B3 is driven
low, an output voltage of 1.0V is selected. The pullup resistor
is connected to the main input voltage. Transitions of the pins
will not affect the output voltage, the state is only checked
during startup.
20.6 UNDERVOLTAGE LOCKOUT (UVLO)
The V
IN voltage is monitored for a supply under voltage con-
dition, for which the operation of the device can not be guar-
anteed. The part will automatically disable Buck 3. To prevent
unstable operation, the undervoltage lockout (UVLO) has a
hysteresis window of about 300 mV. An UVLO will force the
device into the reset state, all internal registers are reset.
Once the supply voltage is above the UVLO hysteresis, the
device will initiate a power-up sequence and then enter the
active state.
Buck 1 and Buck 2 will remain in bypass mode after V
IN pass-
es the UVLO until V
IN reaches approximately 1.9V. When
Buck 2 is set to 1.8V, the voltage will jump from 1.8V to
V
UVLO_FALLING, and then follow VIN.
The LDO and the Comparator will remain functional past the
UVLO threshold until V
IN reaches approximately 2.25V.
20.7 OVERVOLTAGE LOCKOUT (OVLO)
The V
IN voltage is monitored for a supply over voltage condi-
tion, for which the operation of the device cannot be guaran-
teed. The purpose of overvoltage lockout (OVLO) is to protect
the part and all other consumers connected to the PMU out-
puts from any damage and malfunction. Once V
IN rises over
5.7V all the Bucks, and LDO will be disabled automatically.
To prevent unstable operation, the OVLO has a hysteresis
window of about 100 mV. An OVLO will force the device into
the reset state; all internal registers are reset. Once the supply
voltage is below the OVLO hysteresis, the device will initiate
a power-up sequence, and then enter the active state. Oper-
ating maximum input voltage at which parameters are guar-
anteed is 5.5V. Absolute maximum of the device is 6.0V.
20.8 DEVICE STATUS, INTERRUPT ENABLE
The LM10506 has 2 interrupt registers, INTERRUPT EN-
ABLE and INTERRUPT STATUS. These registers can be
read via the serial interface. The interrupts are not latched to
the register and will always represent the current state and
will not be cleared on a read.
If interrupt condition is detected, then corresponding bit in the
INTERRUPT STATUS register (0x0D) is set to '1', and IRQ
output is asserted. There are 5 interrupt generating condi-
tions:
Buck 3 output is over flag level (90% when rising, 85%
when falling)
Buck 2 output is over flag level (90% when rising, 85%
when falling)
Buck 1 output is over flag level (90% when rising, 85%
when falling)
LDO is over flag level (90% when rising, 85% when falling
Comparator input voltage crosses over selected threshold
Reading the interrupt register will not release IRQ output. In-
terrupt generation conditions can be individually enabled or
disabled by writing respective bits in INTERRUPT ENABLE
register (0x0C) to '1' or '0'.
20.9 THERMAL SHUTDOWN (TSD)
The temperature of the silicon die is monitored for an over-
temperature condition, for which the operation of the device
can not be guaranteed. The part will automatically be disabled
if the temperature is too high. The thermal shutdown (TSD)
will force the device into the reset state. In reset, all circuitry
is disabled. To prevent unstable operation, the TSD has a
hysteresis window of about 20°C. Once the temperature has
decreased below the TSD hysteresis, the device will initiate
a powerup sequence and then enter the active state. In the
active state, the part will start up as if for the first time, all
registers will be in their default state.
www.national.com
26
LM10506
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LM10506TMX-A/NOPB | 功能描述:直流/直流开关转换器 Triple Buck & LDO Power Mgmt Unit RoHS:否 制造商:STMicroelectronics 最大输入电压:4.5 V 开关频率:1.5 MHz 输出电压:4.6 V 输出电流:250 mA 输出端数量:2 最大工作温度:+ 85 C 安装风格:SMD/SMT |
| LM10506TMX-C/NOPB | 制造商:Texas Instruments 功能描述:LINEAR IC |
| LM10506TMXNOPB | 制造商:Texas Instruments 功能描述:Power Management Unit 34-Pin Micro SMD T/R |
| LM10507TMX-A/NOPB | 功能描述:Solid State Drives (SSD) PMIC 34-DSBGA (2.82x2.82) 制造商:texas instruments 系列:- 包装:剪切带（CT） 零件状态:有效 应用:固态驱动器（SSD） 电流 - 电源:50μA 电压 - 电源:3 V ~ 5.5 V 工作温度:-30°C ~ 85°C 安装类型:表面贴装 封装/外壳:34-WFBGA，DSBGA 供应商器件封装:34-DSBGA（2.82x2.82） 标准包装:1 |
| LM10520 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:20A Adaptive Voltage Scaling (AVS) Evaluation Board |
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