参数资料
型号: ISPLSI 2032VE-110LTN48
厂商: Lattice Semiconductor Corporation
文件页数: 13/16页
文件大小: 0K
描述: IC PLD ISP 32I/O 10NS 48TQFP
标准包装: 250
系列: ispLSI® 2000VE
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 10.0ns
电压电源 - 内部: 3 V ~ 3.6 V
逻辑元件/逻辑块数目: 8
宏单元数: 32
门数: 1000
输入/输出数: 32
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-TQFP(7x7)
包装: 托盘
其它名称: ISPLSI2032VE-110LTN48
Specifications ispLSI 2032VE
5
USE
2032VE-300
FOR
NEW
DESIGNS
External Timing Parameters
Over Recommended Operating Conditions
tpd1
UNITS
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030A/2032VE
v.0.1
1
3
2
1
tsu2 + tco1
(
)
DESCRIPTION
#
PARAMETER
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
ns
tpd2
A
2
Data Propagation Delay
ns
fmax
A
3
Clock Frequency with Internal Feedback
MHz
fmax (Ext.)
4
Clock Frequency with External Feedback
MHz
fmax (Tog.)
5
Clock Frequency, Max. Toggle
MHz
tsu1
6
GLB Reg. Setup Time before Clock, 4 PT Bypass
ns
tco1
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
ns
th1
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
ns
tsu2
9
GLB Reg. Setup Time before Clock
ns
tco2
A
10
GLB Reg. Clock to Output Delay
ns
th2
11
GLB Reg. Hold Time after Clock
ns
tr1
A
12
Ext. Reset Pin to Output Delay, ORP Bypass
ns
trw1
13
Ext. Reset Pulse Duration
ns
tptoeen
B
14
Input to Output Enable
ns
tptoedis
C
15
Input to Output Disable
ns
tgoeen
B
16
Global OE Output Enable
ns
tgoedis
C
17
Global OE Output Disable
ns
twh
18
External Synchronous Clock Pulse Duration, High
ns
twl
19
External Synchronous Clock Pulse Duration, Low
ns
-225
MIN. MAX.
4.0
225
0.0
3.5
0.0
3.5
2.0
2.0
154
250
2.5
3.0
4.0
5.0
7.0
3.5
6.0
-300
MIN. MAX.
3.0
300
0.0
2.8
0.0
3.0
1.5
1.5
208
333
2.0
2.5
4.5
5.0
3.0
4.5
SELECT
DEVICES
DISCONTINUED
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