参数资料
型号: LM1246AAA/NA
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 音频/视频放大
英文描述: 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP24
封装: PLASTIC, DIP-24
文件页数: 27/51页
文件大小: 2794K
代理商: LM1246AAA/NA
Building Display Pages (Continued)
TABLE 21. Two Byte Communication Mode
ATTRIBUTE Byte
X
0
1
CC[8]
ATT[3:0]
TABLE 22. Sequence of Transmitted Bytes
HALF RANDOM ADDRESS MODE
The Half Random Address mode allows different attribute and character codes to be sent within one transmission in the same
way as the Two Byte Communication mode. The entire 512-character Page ROM is fully accessible in this mode, without the need
to stop and restart transmission. The advantage of Half Random Addressing over the Two Byte mode is that the Page RAM
addresses do not have to be written to in a sequential order. However, the Page RAM addresses cannot be entirely random, as
they must be within one half of the Page RAM. A new transmission must be restarted to switch to another half of the Page RAM.
The Page RAM address is not automatically incremented in this mode. This mode is very useful for modifying character codes
and attributes in the first 256 locations of the Page RAM. The attribute byte is shown in Table 23. Half Random Address Mode,
and the sequence of transmitted bytes is shown in Table 24. Sequence of Transmitted Bytes. Either another LSB address &
attribute & character code or a STOP must follow after each character code.
TABLE 23. Half Random Address Mode
ATTRIBUTE Byte
X
1
0
CC[8]
ATT[3:0]
TABLE 24. Sequence of Transmitted Bytes
FULL RANDOM ADDRESS MODE
The Full Random Address mode is very similar to the Half Random Address mode. However, the advantage is that the Page RAM
addresses can now be entirely random. There is no longer a restriction to only one half of the Page RAM. The Page RAM address
is not automatically incremented in this mode. This is very useful for modifying character codes and attributes anywhere in the
Page RAM without starting a new transmission sequence. The Full Random Address mode is the most flexible mode of
transmission. The attribute byte is shown in Table 25. Full Random Address Mode, and the sequence of transmitted bytes is
shown in Table 26. Sequence of Transmitted Bytes. Either another LSB address & MSB address & attribute & character code or
a STOP must follow after each character code.
TABLE 25. Full Random Address Mode
ATTRIBUTE Byte
X
1
CC[8]
ATT[3:0]
TABLE 26. Sequence of Transmitted Bytes
Control Register Definitions
OSD INTERFACE REGISTERS
Frame Control Register 1:
FRMCTRL1 (0x8400)
autosize
Fade
i/o
trans
clear
win2
win1
OSD
HTD
ASZEN
FEN
TD
CDPR
D2E
D1E
OsE
LM1246
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