参数资料
型号: LM1246AAA/NA
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 音频/视频放大
英文描述: 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP24
封装: PLASTIC, DIP-24
文件页数: 30/51页
文件大小: 2794K
代理商: LM1246AAA/NA
Control Register Definitions (Continued)
Bit 0
This controls the calculation of the ROM signature. Setting this bit causes the ROM to be read
sequentially and a 16-bit checksum calculated over the 256 characters. The sum, modulo 65535, is
stored in the ROM Signature Data Register, and this bit is then automatically cleared.
Bits 7–1
Reserved. These should be set to zero.
ROM Signature Data:
ROMSIGDATAB1 (0x840F)
ROMSIGDATAB0 (0x840E)
16-Bit Checksum
CRC[15:0]
Bits 15–0
This is the checksum of the 256 ROM characters truncated to 16 bits (modulo 65535). All devices
with the same masked ROM will have the same checksum.
Display Window 1 Horizontal Start Address:
HSTRT1 (0x8410)
Window 1 Horizontal Start Location
1H[7:0]
Bits 7–0
There are two possible OSD windows which can be displayed simultaneously or individually. This
register determines the horizontal start position of Window 1 in OSD pixels (not video signal
pixels). The actual position, to the right of the horizontal flyback pulse, is determined by multiplying
this register value by 4 and adding 30. Due to pipeline delays, the first usable start location is
approximately 42 OSD pixels following the horizontal flyback time. For this reason, we recommend
this register be programmed with a number larger than 2, otherwise improper operation may result.
Display Window 1 Vertical Start Address:
VSTRT1 (0x8411)
Window 1 Vertical Start Address
1V[7:0]
Bits 7–0
This register determines the Vertical start position of the Window 1 in constant-height character
lines (not video scan lines). The actual position is determined by multiplying this register value by
2. (Note: each character line is treated as a single auto-height character pixel line, so multiple scan
lines may actually be displayed in order to maintain accurate position relative to the OSD character
cell size. See the Constant Character Height Mechanism section.) This register should be set so
the entire OSD window is within the active video.
Display Window 1 Start Address:
W1STRTADRH (0x8413)
W1STRTADRL (0x8412)
Reserved
Window 1 Start Address
XXXXXXX
1AD[8:0]
Bits 8–0
This register determines the starting address of Display Window 1 in the Display Page RAM. The
power-on default of 0x00 starts Window 1 at the beginning of the Page RAM (0x8000). This first
address location always contains the SL code for the first line of Display Window 1. This register is
new for the LM1246 and allows Window 1 to start anywhere in the Page RAM rather than just at
0x8000. Note that the address this points to in Page RAM must always contain the SL code for the
first line of the window.
Bits 15–9
These bits are reserved and should be set to zero.
Display Window 1 Column Width:
COLWIDTH1B3 (0x8417)
COLWIDTH1B2 (0x8416)
Window 1 Column Width - High Bytes
COL[31:16]
LM1246
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相关代理商/技术参数
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