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参数资料
| 型号： | LM12H458CIVX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 20/36页 |
| 文件大小： | 1195K |
| 代理商： | LM12H458CIVX |
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2.0 Internal User-Programmable
Registers (Continued)
Bits 12–15 are used to store the user-programmable acqui-
sition time. The Sequencer keeps the internal S/H in the
acquisition mode for a fixed number of clock cycles (nine
clock cycles, for 12-bit + sign conversions and two clock
cycles for 8-bit + sign conversions or “watchdog” compari-
sons) plus a variable number of clock cycles equal to twice
the value stored in Bits 12–15. Thus, the S/H’s acquisition
time is (9 + 2D) clock cycles for 12-bit + sign conversions
and (2 + 2D) clock cycles for 8-bit + sign conversions or
“watchdog” comparisons, where D is the value stored in Bits
12–15. The minimum acquisition time compensates for the
typical internal multiplexer series resistance of 2 k
, and any
additional delay created by Bits 12–15 compensates for
source resistances greater than 60
(100). (For this acqui-
sition time discussion, numbers in ( ) are shown for the
LM12(H)454/8 operating at 5 MHz.) The necessary acquisi-
tion time is determined by the source impedance at the
multiplexer input. If the source resistance (R
S) < 60
(100)
and the clock frequency is 8 MHz, the value stored in bits
12–15 (D) can be 0000. If R
S > 60
(100), the following
equations determine the value that should be stored in
bits 12–15.
D=0.45xR
S xfCLK
for 12-bits + sign
D=0.36xR
S xfCLK
for 8-bits + sign and “watchdog”
R
S is in k
and f
CLK is in MHz. Round the result to the next
higher integer value. If D is greater than 15, it is advisable to
lower the source impedance by using an analog buffer be-
tween the signal source and the LM12(H)458’s multiplexer
inputs. The value of D can also be used to compensate for
the settling or response time of external processing circuits
connected between the LM12454’s MUXOUT and S/H IN
pins.
Instruction RAM “01”
The second Instruction RAM section is selected by placing a
“01” in Bits 8 and 9 of the Configuration register.
Bits 0–7 hold “watchdog” limit #1. When Bit 11 of Instruction
RAM “00” is set to a “1”, the LM12(H)454/8 performs a
“watchdog” comparison of the sampled analog input signal
with the limit #1 value first, followed by a comparison of the
same sampled analog input signal with the value found in
limit #2 (Instruction RAM “10”).
Bit 8 holds limit #1’s sign.
Bit 9’s state determines the limit condition that generates a
“watchdog” interrupt. A “1” causes a voltage greater than
limit #1 to generate an interrupt, while a “0” causes a voltage
less than limit #1 to generate an interrupt.
Bits 10–15 are not used.
Instruction RAM “10”
The third Instruction RAM section is selected by placing a
“10” in Bits 8 and 9 of the Configuration register.
Bits 0–7 hold “watchdog” limit #2. When Bit 11 of Instruction
RAM “00” is set to a “1”, the LM12(H)454/8 performs a
“watchdog” comparison of the sampled analog input signal
with the limit #1 value first (Instruction RAM “01”), followed
by a comparison of the same sampled analog input signal
with the value found in limit #2.
Bit 8 holds limit #2’s sign.
Bit 9 ’s state determines the limit condition that generates a
“watchdog” interrupt. A “1” causes a voltage greater than
limit #2 to generate an interrupt, while a “0” causes a voltage
less than limit #2 to generate an interrupt.
Bits 10–15 are not used.
2.2 CONFIGURATION REGISTER
The Configuration register, 1000 (A4–A1, BW = 0) or 1000x
(A4–A0, BW = 1) is a 16-bit control register with read/write
capability. It acts as the LM12454’s and LM12(H)458’s “con-
trol panel” holding global information as well as start/stop,
reset, self-calibration, and stand-by commands.
Bit 0 is the START/STOP bit. Reading Bit 0 returns an
indication of the Sequencer’s status. A “0” indicates that the
Sequencer is stopped and waiting to execute the next in-
struction. A “1” shows that the Sequencer is running. Writing
a “0” halts the Sequencer when the current instruction has
finished execution. The next instruction to be executed is
pointed to by the instruction pointer found in the status
register. A “1” restarts the Sequencer with the instruction
currently pointed to by the instruction pointer. (See Bits 8–10
in the Interrupt Status register.)
Bit 1 is the LM12(H)454/8’s system RESET bit. Writing a “1”
to Bit 1 stops the Sequencer (resetting the Configuration
register’s START/STOP bit), resets the Instruction pointer to
“000” (found in the Interrupt Status register), clears the Con-
version FIFO, and resets all interrupt flags. The RESET bit
will return to “0” after two clock cycles unless it is forced high
by writing a “1” into the Configuration register’s Standby bit.
A reset signal is internally generated when power is first
applied to the part. No operation should be started until the
RESET bit is “0”.
Writing a “1” to Bit 2 initiates an auto-zero offset voltage
calibration. Unlike the eight-sample auto-zero calibration
performed during the full calibration procedure, Bit 2 initiates
a “short” auto-zero by sampling the offset once and creating
a correction coefficient (full calibration averages eight
samples of the converter offset voltage when creating a
correction coefficient). If the Sequencer is running when Bit 2
is set to “1”, an auto-zero starts immediately after the con-
clusion of the currently running instruction. Bit 2 is reset
automatically to a “0” and an interrupt flag (Bit 3, in the
Interrupt Status register) is set at the end of the auto-zero
(76 clock cycles). After completion of an auto-zero calibra-
tion, the Sequencer fetches the next instruction as pointed to
by the Instruction RAM’s pointer and resumes execution. If
the Sequencer is stopped, an auto-zero is performed imme-
diately at the time requested.
Writing a “1” to Bit 3 initiates a complete calibration process
that includes a “long” auto-zero offset voltage correction (this
calibration averages eight samples of the comparator offset
voltage when creating a correction coefficient) followed by
an ADC linearity calibration. This complete calibration is
started after the currently running instruction is completed if
the Sequencer is running when Bit 3 is set to “1”. Bit 3 is
reset automatically to a “0” and an interrupt flag (Bit 4, in the
Interrupt Status register) will be generated at the end of the
calibration procedure (4944 clock cycles). After completion
of a full auto-zero and linearity calibration, the Sequencer
fetches the next instruction as pointed to by the Instruction
RAM’s pointer and resumes execution. If the Sequencer is
stopped, a full calibration is performed immediately at the
time requested.
Bit 4 is the Standby bit. Writing a “1” to Bit 4 immediately
places the LM12(H)454/8 in Standby mode. Normal opera-
tion returns when Bit 4 is reset to a “0”. The Standby com-
LM12454/LM12458/LM12H458
www.national.com
27
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LM12H458CIVX/NOPB | 功能描述:IC ACQUISITION SYS 12BIT 44-PLCC RoHS:是 类别:集成电路 (IC) >> 数据采集 - ADCs/DAC - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:数据采集系统（DAS） 分辨率（位）:16 b 采样率（每秒）:21.94k 数据接口:MICROWIRE?，QSPI?，串行，SPI? 电压电源:模拟和数字 电源电压:1.8 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（6x6） 包装:托盘 |
| LM12H458CMEL/883 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Single-Ended Data Acquisition System |
| LM12H458MEL/883 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:12-Bit Sign Data Acquisition System with Self-Calibration |
| LM12H458MW/883 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Single-Ended Data Acquisition System |
| LM12L438CIV | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Sign Data Acquisition System with Serial I/O and Self-Calibration |
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