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参数资料
| 型号： | LM2316SLBX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, CQCC16 |
| 封装： | CSP-16 |
| 文件页数： | 19/19页 |
| 文件大小： | 300K |
| 代理商： | LM2316SLBX |
1.0 Functional Description (Continued)
1.3 FUNCTION AND INITIALIZATION LATCHES
Both the function and initialization latches write to the same registers. (See Section 1.7.1 DEVICE PROGRAMMING AFTER
FIRST APPLYING V
CC section for initialization latch description.)
TABLE 1. Programmable Modes
C1
C2
F1
F2
F3–5
F6
F7
F8
0
1
COUNTER
POWER DOWN
FoLD
PD
CP
FASTLOCK
RESET
CONTROL
POLARITY
TRI-STATE
ENABLE
F9
F10
F11–14
F15–F17
F18
FAST-
TIMEOUT
TEST
POWER
LOCK
COUNTER
MODES
DOWN
CONTROL
ENABLE
VALUE
MODE
TABLE 2. Mode Select Truth Table
REGISTER
LEVEL
COUNTER
RESET
POWER
DOWN
PHASE
CP
TRI-STATE
DETECTOR
POLARITY
0
RESET
POWERED
NEGATIVE
NORMAL
DISABLED
UP
OPERATION
1
RESET
POWERED
POSITIVE
TRI-STATE
ENABELED
DOWN
FUNCTION DESCRIPTION
F1. The Counter Reset enable mode bit F1, when activated, allows the reset of both N and R counters. Upon powering up, the
F1 bit needs to be disabled, then the N counter resumes counting in “close” alignment with the R counter. (The maximum error
is one prescalar cycle).
F2. Refer to Section 1.3.1 POWERDOWN OPERATION section.
F3–5. Controls output of FoLD pin. See FoLD truth table. See
Table 4.
F6. Phase Detector Polarity. Depending upon VCO characteristics, F6 bit should be set accordingly. When VCO characteristics
are positive F6 should be set HIGH; When VCO characteristics are negative F6 should be set LOW
F7. Charge Pump TRI-STATE is set using bit F7. For normal operation this bit is set to zero.
F8. When the FastLock Enable bit is set the part is forced into one of the four FastLock modes. See description in
Table 5,
FastLock Decoding.
F9. The FastLock Control bit determines the mode of operation when in FastLock (F8 = 1). When not in FastLock mode, FL
o
can be used as a general purpose output controlled by this bit. For F9 = 1, FL
o is HIGH and for F9 = 0, FLo is LOW. See Table
5 for truth table.
F10. Timeout Counter Enable bit is set to 1 to enable the timeout counter. See
Table 5 for truth table.
F11–14. FastLock Timeout Counter is set using bits F11-14.
Table 6 for counter values.
F15–17. Function bits F15–F17 are for Test Modes, and should be set to 0 for normal use.
F18. Refer to Section 1.3.1 POWERDOWN OPERATION section.
DS100127-7
LMX2306/LMX2316/LMX2326
www.national.com
9
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