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参数资料
| 型号： | LM2316SLBX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, CQCC16 |
| 封装： | CSP-16 |
| 文件页数： | 3/19页 |
| 文件大小： | 300K |
| 代理商： | LM2316SLBX |
1.0 Functional Description (Continued)
1.3.2 LOCK DETECT OUTPUT CHARACTERISTICS
Output provided to indicate when the VCO frequency is in “lock.” When the loop is locked and the open drain lock detect mode
is selected, the pin’s output is HIGH, with narrow pulses LOW. When digital lock detect is selected, the output will be HIGH when
the absolute phase error is < 15 ns for three or five consecutive phase frequency detector reference cycles, depending on the
value of R[19]. Once lock is detected the output stays HIGH unless the absolute phase error exceeds 30 ns for a single reference
cycle. Setting the charge pump to TRI-STATE or power down (bits F2, F18) will reset the digital lock detect to the unlocked state.
The LD precision bit, R[19], will select five consecutive reference cycles, instead of three, for entering the locked state when R[19]
= HIGH.
1.3.3 LOCK DETECT FILTER CALCULATION
The component values for the open drain lock detect filter can be determined after assessing the qualifications for an in-lock
condition. The in-lock condition can be specified as being a particular number (N) of consecutive reference cycles or duration (D)
wherein the phase detector phase error is some factor less than the reference period. In an example where the phase detector
reference period is 10 kHz, one might select the threshold for in-lock as occurring when 5 consecutive phase comparisons have
elapsed where the phase errors are a 1000 times shorter than the reference period (100 ns). Here, N = 5 and F = 1000.
For the lock detect filter shown in
Figure 1, when used in conjunction with a open drain (active sink only) lock detect output, the
resistor value for R2 would be chosen to be a factor of F * R1. Thus, if resistor R1 were pulled low for only 1/1000th of the
reference cycle period, its “effective” resistance would be on par with R2. The two resistors for that duty cycle condition on
average appear to be two 1000x R1 resistors connected across the supply voltage with their common node voltage (Vc) at V
CC/2.
Phase errors larger than 1/1000th of the reference cycle period would drag the average voltage of node Vc below V
CC/2 indicating
an out-of-lock status. If the time constant of R2 * C1 is now calculated to be N * the reference period (500 s), then the voltage
of node Vc would fall below V
CC/2 only after 5 consecutive phase errors whose average pulse width was greater than 100 ns.
1.3.4 FastLock MODES
FastLock enables the designer to achieve both fast frequency transitions and good phase noise performance by dynamically
changing the PLL loop bandwidth. The FastLock modes allow wide band PLL fast locking with seemless transition to a low phase
noise narrow band PLL. Consistent gain and phase margins are maintained by simultaneously changing charge pump current
magnitude, counter values, and loop filter damping resistor. The four FastLock modes in
Table 5 are similar to the technique used
in National Semiconductor’s LMX 233X series Dual Phase Locked Loops and are selected by F9, F10, and N19 when F8 is HIGH.
Modes 1 and 2 change loop bandwidth by a factor of two while modes 3 and 4 change the loop bandwidth by a factor of 4. Modes
1 and 2 increase charge pump magnitude by a factor of 4 and should use R2’=R2 for consistent gain and phase margin. Modes
3 and 4 increase charge pump magnitude and decrease the counter values by a factor of 4. R2’ = 13 R2 should be used for
consistent stability margin in modes 3 and 4. When F8 is LOW, the FastLock modes are disabled, F9 controls only the FL
o output
level (FL
o = F9), and N19 determines the charge pump current magnitude (N19=LOW→ICPo = 250 A, N19=HIGH→ICPo =
1 mA).
DS100127-13
FIGURE 1. Typical Lock Detect Circuit
LMX2306/LMX2316/LMX2326
www.national.com
11
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