参数资料
型号: LM3421MHX/NOPB
厂商: National Semiconductor
文件页数: 3/67页
文件大小: 0K
描述: IC LED DRVR HP CONS CURR 16TSSOP
产品培训模块: LED Design Solutions
标准包装: 2,500
系列: PowerWise®
恒定电流:
拓扑: PWM,SEPIC,降压(降压),升压(升压)
输出数: 1
内部驱动器:
类型 - 主要: 车载
类型 - 次要: 高亮度 LED(HBLED)
频率: 2MHz
电源电压: 4.5 V ~ 75 V
输出电压: 3 V ~ 72 V
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
供应商设备封装: 16-TSSOP-EP
包装: 带卷 (TR)
工作温度: -40°C ~ 125°C
其它名称: LM3421MHX
PIN DESCRIPTIONS (continued)
SNVS574E – JULY 2008 – REVISED MAY 2013
LM3423
LM3421
Name
Description
Function
Connect a PWM signal for dimming as detailed in the PWM
8
8
nDIM
Dimming Input /
Under-Voltage Protection
DIMMING section and/or a resistor divider from V IN to program input
under-voltage lockout (UVLO). Turn-on threshold is 1.24V and
hysteresis for turn-off is provided by 23 μA current source.
9
10
11
12
13
14
15
16
-
-
-
-
9
10
11
12
FLT
TIMR
LRDY
DPOL
DDRV
PGND
GATE
V CC
Fault Flag
Fault Timer
LED Ready Flag
Dim Polarity
Dim Gate Drive Output
Power Ground
Main Gate Drive Output
Internal Regulator Output
Connect to pull-up resistor from VIN and N-channel MosFET open
drain output is high when a fault condition is latched by the timer.
Connect a capacitor to AGND to set the time delay before a sensed
fault condition is latched.
Connect to pull-up resistor from VIN and N-channel MosFET open
drain output pulls down when the LED current is not in regulation.
Connect to AGND if dimming with a series P-channel MosFET or
leave open when dimming with series N-channel MosFET.
Connect to the gate of the dimming MosFET.
Connect to AGND through the DAP copper pad to provide ground
return for GATE and DDRV.
Connect to the gate of the main switching MosFET.
Bypass with 2.2 μF–3.3 μF ceramic capacitor to PGND.
Connect to the drain of the main N-channel MosFET switch for R DS-
17
13
IS
Main Switch Current Sense
ON sensing or to a sense resistor installed in the source of the same
device.
18
19
20
DAP (21)
14
15
16
DAP (17)
RPD
HSP
HSN
DAP
Resistor Pull Down
LED Current Sense Positive
LED Current Sense Negative
Thermal PAD on bottom of IC
Connect the low side of all external resistor dividers (V IN UVLO, OVP)
to implement “zero-current” shutdown.
Connect through a series resistor to the positive side of the LED
current sense resistor.
Connect through a series resistor to the negative side of the LED
current sense resistor.
Star ground, connecting AGND and PGND. For thermal
considerations please refer to (1) .
(1)
Junction-to-ambient thermal resistance is highly board-layout dependent. The numbers listed in the table are given for an reference
layout wherein the 16L TSSOP package has its EP pad populated with 9 vias and the 20L TSSOP has its EP pad populated with 12
vias. In applications where high maximum power dissipation exists, namely driving a large MosFET at high switching frequency from a
high input voltage, special care must be paid to thermal dissipation issues during board design. In high-power dissipation applications,
the maximum ambient temperature may have to be derated. Maximum ambient temperature (T A-MAX ) is dependent on the maximum
operating junction temperature (T J-MAX-OP = 125°C for Q1, or 150°C for Q0), the maximum power dissipation of the device in the
application (P D-MAX ), and the junction-to ambient thermal resistance of the package in the application ( θ JA ), as given by the following
equation: T A-MAX = T J-MAX-OP – ( θ JA × P D-MAX ). In most applications there is little need for the full power dissipation capability of this
advanced package. Under these circumstances, no vias would be required and the thermal resistances would be 104 °C/W for the 16L
TSSOP and 86.7 °C/W for the 20L TSSOP. It is possible to conservatively interpolate between the full via count thermal resistance and
the no via count thermal resistance with a straight line to get a thermal resistance for any number of vias in between these two limits.
Copyright ? 2008–2013, Texas Instruments Incorporated
3
Product Folder Links: LM3421 LM3421-Q1 LM3423 LM3423-Q1
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