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| 型号： | LM3668SD-3.3/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 2.05 A DUAL SWITCHING CONTROLLER, 2500 kHz SWITCHING FREQ-MAX, DSO12 |
| 封装： | ROHS COMPLIANT, LLP-12 |
| 文件页数： | 15/20页 |
| 文件大小： | 2497K |
| 代理商： | LM3668SD-3.3/NOPB |
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
PV
IN, VDD Pin, SW1, SW2 & VOUT:
Voltage to SGND & PGND
0.2V to +6.0V
FB, EN,MODE,SYNC pin:
(PGND &
SGND-0.2V) to
(PV
IN + 0.2)
PGND to SGND
-0.2V to 0.2V
Continuous Power Dissipation
(Note 3)
Internally Limited
Maximum Junction Temperature
(T
J-MAX)
+125°C
Storage Temperature Range
65°C to +150°C
Maximum Lead Temperature
(Soldering, 10 sec)
+260°C
Operating Ratings
Input Voltage Range
2.5V to 5.5V
Recommended Load Current
0mA to 1A
Junction Temperature (T
J) Range
40°C to +125°C
Ambient Temperature (T
A) Range
(Note 3)
40°C to +85°C
Thermal Properties
Junction-to-Ambient Thermal Resistance (
θ
JA),
34°C/W
Leadless Lead frame Package (Note 5)
Electrical Characteristics (Notes 6, 7) Limits in standard typeface are for T
J = +25°C. Limits in boldface type
apply over the full operating ambient temperature range (40°C
≤ = T
A ≤ +85°C). Unless otherwise noted: specifications apply to
the LM3668. V
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
FB
Feedback Voltage
(Note 7)
-3
3
%
I
LIM
Switch Peak Current Limit
Open loop(Note 2)
1.6
1.85
2.05
A
I
SHDN
Shutdown Supply Current
EN =0V
0.01
1
A
I
Q_PFM
DC Bias Current in PFM
No load, device is not switching
(FB Forced higher than
programmed output voltage)
45
60
A
I
Q_PWM
DC Bias Current in PWM
PWM Mode, No Switching
600
750
A
R
DSON(P)
Pin-Pin Resistance for PFET
Switches P1 and P2
130
180
m
R
DSON(N)
Pin-Pin Resistance for NFET
Switches N1 and N2
100
150
m
F
OSC
Internal Oscillator Frequency
PWM Mode
1.9
2.2
2.5
MHz
F
SYNC
Sync Frequency Range
V
IN = 3.6V
1.6
2.7
MHz
V
IH
Logic High Input for EN, MODE/
SYNC pins
1.1
V
IL
Logic Low Input for EN, MODES/
SYNC pins
0.4
V
I
EN, MODE, SYNC
EN,MODES/SYNC pin Input Current
0.3
1
A
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 2:
Electrical Characteristic table reflects open loop data (FB = 0V and current drawn from SW pin ramped up until cycle by cycle current limits is activated).
Closed loop current limit is the peak inductor current measured in the application circuit by increasing output current until output voltage drops by 10%.
Note 3:
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T
A-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125C), the maximum power
dissipation of the device in the application (P
D-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the
following equation: T
A-MAX = TJ-MAX-OP – (θJA × PD-MAX).
Note 4:
The Human body model is a 100 pF capacitor discharged through a 1.5 k
resistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin. MIL-STD-883 3015.7
Note 5:
Junction-to-ambient thermal resistance (
θ
JA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the
JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 101.6mm x 76.2mm x 1.6mm. Thickness of the copper layers are 2oz/1oz/1oz/
2oz. The middle layer of the board is 60mm x 60mm. Ambient temperature in simulation is 22°C, still air.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special
care must be paid to thermal dissipation issues in board design.
Note 6:
All voltage is with respect to SGND.
Note 7:
Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 8:
C
IN and COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
www.national.com
4
LM3668
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