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参数资料
| 型号： | LM5025CSD |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, DSO16 |
| 封装： | LLP-16 |
| 文件页数： | 10/16页 |
| 文件大小： | 362K |
| 代理商： | LM5025CSD |
Pin
Name
Description
Application Information
8
OUT_A
Main output driver
Output of the main switch PWM output gate driver.
Output capability of 3A peak sink current.
9
OUT_B
Active Clamp output driver
Output of the Active Clamp switch gate driver. Capable
of 1.25A peak sink current..
10
PGND
Power ground
Connect directly to analog ground.
11
AGND
Analog ground
Connect directly to power ground. For the LLP package
option the exposed pad is electrically connected to
AGND.
12
SS
Soft-start control
An external capacitor and an internal 90 A current
source set the softstart ramp. The SS current source is
reduced to 1 A initially following a CS2 over-current
event or an over temperature event.
13
COMP
Input to the Pulse Width Modulator
An internal 5 k
resistor pull-up is provided on this pin.
The external opto-coupler sinks current from COMP to
control the PWM duty cycle.
14
RT
Oscillator timing resistor pin
An external resistor connected from RT to ground sets
the internal oscillator frequency.
15
SYNC
Oscillator UP/DOWN synchronization input
The internal oscillator can be synchronized to an
external clock with a frequency 20% lower than the
internal oscillator’s free running frequency. There is no
constraint on the maximum sync frequency.
16
UVLO
Line Under-Voltage shutdown
An external voltage divider from the power source sets
the shutdown comparator levels. The comparator
threshold is 2.5V. Hysteresis is set by an internal
current source (20 A) that is switched on or off as the
UVLO pin potential crosses the 2.5V threshold.
-
EP
Exposed PAD, underside of the LLP package
option
Internally bonded to the die substrate. Connect to GND
potential for low thermal impedance.
3
www.national.com
LM5025C
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