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参数资料
| 型号： | LM5025CSD |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, DSO16 |
| 封装： | LLP-16 |
| 文件页数： | 16/16页 |
| 文件大小： | 362K |
| 代理商： | LM5025CSD |
Detailed Operating Description
The LM5025C is a functional variant of the LM5025 active
clamp PWM controller. The functional differences of the
LM5025C are:
The maximum duty cycle of the LM5025C is increased from
80% to 91%. The soft-start capacitor charging current is in-
creased from 20 A to 90 A. The V
CC regulator current limit
threshold is increased from 25 mA to 55 mA.
The CS1 and CS2 current limit thresholds have been in-
creased to 0.5V (same as LM5025A).
The internal CS2 filter discharge device has been disabled
and no longer operates each clock cycle (same as LM5025A).
The internal V
CC and VREF regulators continue to operate
when the line UVLO pin is below threshold (same as
LM5025A).
The LM5025C PWM controller contains all of the features
necessary to implement power converters utilizing the Active
Clamp Reset technique. The device can be configured to
control either a P-Channel clamp switch or an N-Channel
clamp switch. With the active clamp technique higher effi-
ciencies and greater power densities can be realized com-
pared to conventional catch winding or RDC clamp / reset
techniques. Two control outputs are provided, the main power
switch control (OUT_A) and the active clamp switch control
(OUT_B). The active clamp output can be configured for ei-
ther a guaranteed overlap time (for P-Channel switch appli-
cations) or a guaranteed dead time (for N_Channel applica-
tions). The two internal compound gate drivers parallel both
MOS and Bipolar devices, providing superior gate drive char-
acteristics. This controller is designed for high-speed opera-
tion including an oscillator frequency range up to 1MHz and
total PWM and current sense propagation delays less than
100ns. The LM5025C includes a high-voltage start-up regu-
lator that operates over a wide input range of 13V to 90V.
Additional features include: Line Under Voltage Lockout (UV-
LO), softstart, oscillator UP/DOWN sync capability, precision
reference and thermal shutdown.
High Voltage Start-Up Regulator
The LM5025C contains an internal high voltage start-up reg-
ulator that allows the input pin (V
IN) to be connected directly
to the line voltage. The regulator output is internally current
limited to 55 mA. When power is applied, the regulator is en-
abled and sources current into an external capacitor connect-
ed to the V
CC pin. The recommended capacitance range for
the V
CC regulator is 0.1 F to 100 F. When the voltage on
the V
CC pin reaches the regulation point of 7.6V and the in-
ternal voltage reference (REF) reaches its regulation point of
5V, the controller outputs are enabled. The outputs will remain
enabled until V
CC falls below 6.2V or the line Under Voltage
Lock Out detector indicates that V
IN is out of range. In typical
applications, an auxiliary transformer winding is connected
through a diode to the V
CC pin. This winding must raise the
V
CC voltage above 8V to shut off the internal start-up regula-
tor. Powering V
CC from an auxiliary winding improves effi-
ciency while reducing the controller power dissipation.
When the converter auxiliary winding is inactive, external cur-
rent draw on the V
CC line should be limited so the power
dissipated in the start-up regulator does not exceed the max-
imum power dissipation of the controller.
An external start-up regulator or other bias rail can be used
instead of the internal start-up regulator by connecting the
V
CC and the VIN pins together and feeding the external bias
voltage into the two pins.
Line Under-Voltage Detector
The LM5025C contains a line Under Voltage Lock Out (UV-
LO) circuit. An external set-point voltage divider from Vin to
GND, sets the operational range of the converter. The divider
must be designed such that the voltage at the UVLO pin will
be greater than 2.5V when Vin is in the desired operating
range. If the undervoltage threshold is not met, both outputs
are disabled,all other functions of the controller remain active.
UVLO hysteresis is accomplished with an internal 20 uA cur-
rent source that is switched on or off into the impedance of
the set-point divider. When the UVLO threshold is exceeded,
the current source is activated to instantly raise the voltage at
the UVLO pin. When the UVLO pin voltage falls below the
2.5V threshold, the current source is turned off causing the
voltage at the UVLO pin to fall. The UVLO pin can also be
used to implement a remote enable / disable function. Pulling
the UVLO pin below the 2.5V threshold disables the PWM
outputs.
PWM Outputs
The relative phase of the main (OUT_A) and active clamp
outputs (OUT_B) can be configured for the specific applica-
tion. For active clamp configurations utilizing a ground refer-
enced P-Channel clamp switch, the two outputs should be in
phase with the active clamp output overlapping the main out-
put. For active clamp configurations utilizing a high side N-
Channel switch, the active clamp output should be out of
phase with main output and there should be a dead time be-
tween the two gate drive pulses. A distinguishing feature of
the LM5025C is the ability to accurately configure either dead
time (both off) or overlap time (both on) of the gate driver out-
puts. The overlap / deadtime magnitude is controlled by the
resistor value connected to the TIME pin of the controller. The
opposite end of the resistor can be connected to either REF
for deadtime control or GND for overlap control. The internal
configuration detector senses the connection and configures
the phase relationship of the main and active clamp outputs.
The magnitude of the overlap/dead time can be calculated as
follows:
Overlap Time (ns) = 2.8 x R
SET - 1.2
Dead Time (ns) = 2.9 x R
SET +20
R
SET in k, Time in ns
9
www.national.com
LM5025C
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