参数资料
型号: LM5025CSDX
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, DSO16
封装: LLP-16
文件页数: 13/16页
文件大小: 362K
代理商: LM5025CSDX
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Soft-Start
Soft-start Current Source
Normal
65
90
115
A
Soft-start Current Source
following a CS2 event
0.5
1
1.5
A
Oscillator
Frequency1
T
A = 25°C
T
J = Tlow to Thigh
180
175
200
220
225
kHz
Frequency2
RT = 10.8 k
510
580
650
kHz
Sync threshold
2
V
Min Sync Pulse Width
100
ns
Sync Frequency Range
160
kHz
PWM Comparator
Delay to Output
COMP step 5V to 0V
Time to onset of OUT_A
transition low
40
ns
Duty Cycle Range
0
91
%
COMP to PWM Offset
0.7
1
1.3
V
COMP Open Circuit
Voltage
4.3
5.9
V
COMP Short Circuit
Current
COMP = 0V
0.6
1
1.4
mA
Volt x Second Clamp
Ramp Clamp Level
Delta RAMP measured from
onset of OUT_A to Ramp peak.
COMP = 5V
2.4
2.5
2.6
V
UVLO Shutdown
Undervoltage Shutdown
Threshold
2.44
2.5
2.56
V
Undervoltage Shutdown
Hysteresis
16
20
24
A
Output Section
OUT_A High Saturation
MOS Device @ Iout = -10mA,
5
10
OUTPUT_A Peak Current
Sink
Bipolar Device @ Vcc/2
3
A
OUT_A Low Saturation
MOS Device @ Iout = 10mA,
6
9
OUTPUT_A Rise Time
C
gate = 2.2nF
20
ns
OUTPUT_A Fall Time
C
gate = 2.2nF
15
ns
OUT_B High Saturation
MOS Device @ Iout = -10mA,
10
20
OUTPUT_B Peak Current
Sink
Bipolar Device @ Vcc/2
1
A
OUT_B Low Saturation
MOS Device @ Iout = 10mA,
12
18
OUTPUT_B Rise Time
C
gate = 1nF
20
ns
OUTPUT_B Fall Time
C
gate = 1nF
15
ns
Output Timing Control
Overlap Time
R
SET = 38 k connected to
GND, 50% to 50% transitions
75
105
135
ns
Deadtime
R
SET = 29.5 k connected to
REF, 50% to 50% transitions
75
105
135
ns
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6
LM5025C
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