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TSSOP
Pin
LLP Pin
Name
Description
Application Information
3
27
RAMP
Input to PWM Comparator
Modulation ramp for the PWM comparator. This ramp can be a
signal representative of the primary current (current mode) or
proportional to the input voltage (feed-forward voltage mode).
This pin is reset to GND at the end of every cycle.
4
28
CS
Current Sense Input
If CS exceeds 750mV the PWM output pulse will be terminated,
entering cycle-by-cycle current limit. An internal switch holds CS
low for 40nS after either output switches high to blank leading
edge transients.
5
1
SLOPE
Slope Compensation Current
A ramping current source from 0 to 100A is provided for slope
compensation in current mode control. This pin can be connected
through an appropriate resistor to the CS pin to provide slope
compensation. If slope compensation is not required, SLOPE
must be tied to ground.
6
2
COMP
Input to the Pulse Width Modulator An external opto-coupler connected to the COMP pin sources
current into an internal NPN current mirror. The PWM duty cycle
is at maximum with zero input current, while 1mA reduces the
duty cycle to zero. The current mirror improves the frequency
response by reducing the AC voltage across the opto-coupler.
7
3
REF
Output of a 5V reference
Maximum output current is 15mA. Locally decouple with a 0.1F
capacitor.
8
4
RT/SYNC Oscillator Frequency Control and
Frequency Synchronization
The resistance connected between RT and AGND sets the
oscillator frequency. Synchronization is achieved by AC coupling
a pulse to the RT/SYNC pin that raises the voltage at least 1.5V
above the 2V nominal bias level.
9
5
AGND
Analog Ground
Connect directly to the Power Ground.
10
6
RD1
Synchronous Rectifier Leading
Edge Delay
The resistance connected between RD1 and AGND sets the
delay from the falling edge of SR1 or SR2 and the rising edge of
HO2/LO1 or HO1/LO2 respectively.
11
7
RD2
Synchronous Rectifier Trailing
Edge Delay
The resistance connected between RD2 and AGND sets the
delay from the falling edge of HO1/LO2 or HO2/LO1 and the rising
edge of SR2 or SR1 respectively.
12
8
RES
Restart Timer
Whenever the CS pin exceeds the 750mV cycle-cycle current
limit threshold, 30A current is sourced into the RES capacitor for
the remainder of the PWM cycle. If the RES capacitor voltage
reaches 1.0V, the SS capacitor is discharged to disable the HO1,
HO2, LO1, LO2 and SR1, SR2 outputs. The SS pin is held low
until the voltage on the RES capacitor has been ramped between
2V and 4V eight times by 10A charge and 5A discharge
currents. After the delay sequence, the SS capacitor is released
to initiate a normal start-up sequence.
13
9
SS
Soft-Start Input
An internal 20A current source charges the SS pin during start-
up. The input to the PWM comparator gradually rises as the SS
capacitor charges to steadily increase the PWM duty cycle.
Pulling the SS pin to a voltage below 200mV stops PWM pulses
at HO1,2 and LO1,2 and turns off the synchronous rectifier FETs
to a low state.
14
10
SSSR
Secondary Side Soft-Start
An external capacitor and an internal 20A current source set the
soft-start ramp for the synchronous rectifiers. The SSSR
capacitor charge-up is enabled after the first output pulse and
SS>2V and Icomp <800A
15
11
SSOFF
Soft-Stop Disable
When SS OFF pin is connected to the AGND, the LM5045 soft-
stops in the event of a VIN UVLO and Hiccup mode current limit
condition. If the SSOFF pin is connected to REF pin, the controller
hard-stops on any fault condition. Refer Table 1 for more details.
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4
LM5045