- 您现在的位置：买卖IC网 > PDF目录67756 > LM5117PMH (NATIONAL SEMICONDUCTOR CORP) SWITCHING CONTROLLER, 530 kHz SWITCHING FREQ-MAX, PDSO20 PDF资料下载
参数资料
| 型号： | LM5117PMH |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 530 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封装： | TSSOP-20 |
| 文件页数： | 9/32页 |
| 文件大小： | 844K |
| 代理商： | LM5117PMH |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页
HO and LO Drivers
The LM5117 contains high current NMOS drivers and an as-
sociated high-side level shifter to drive the external high-side
NMOS device. This high-side gate driver works in conjunction
with an external diode D
HB, and bootstrap capacitor CHB. A
0.1
μF or larger ceramic capacitor, connected with short traces
between the HB and SW pin, is recommended. During the off-
time of the high-side NMOS driver, the SW pin voltage is
approximately 0V and the C
HB is charged from VCC through
the D
HB. When operating with a high PWM duty cycle, the
high-side NMOS device is forced off each cycle for 320ns to
ensure that C
HB is recharged.
The LO and HO outputs are controlled with an adaptive dead-
time methodology which insures that both outputs are never
enabled at the same time. When the controller commands HO
to be enabled, the adaptive dead-time logic first disables LO
and waits for the LO voltage to drop. HO is then enabled after
a small delay (LO Fall to HO Rise Delay). Similarly, the LO
turn-on is delayed until the HO voltage has discharged. LO is
then enabled after a small delay (HO Fall to LO Rise Delay).
This technique insures adequate dead-time for any size
NMOS device, especially when VCC is supplied by a higher
external voltage source. The adaptive dead-time circuitry
monitors the voltages of HO and LO outputs and insures the
dead-time between the HO and LO outputs. Adding a gate
resister, R
GH or RGL, may decrease the effective dead-time.
Care should be exercised in selecting an output NMOS device
with the appropriate threshold voltage, especially if VCC is
supplied by an external bias supply voltage below the VCC
regulation level. During startup at low input voltages, the low-
side NMOS device gate plateau voltage should be lower than
the VCC under-voltage lockout threshold. Otherwise, there
may be insufficient VCC voltage to completely enhance the
NMOS device as the VCC under-voltage lockout is released
during startup. If the high-side NMOS drive voltage is lower
than the high-side NMOS device gate plateau voltage during
startup, the regulator may not start or it may hang up mo-
mentarily in a high power dissipation state. This condition can
be addressed by selecting an NMOS device with a lower
threshold voltage. This situation can be avoided if the mini-
mum input voltage programmed by the UVLO resistor is
above the VCC regulation level.
Current Monitor
The LM5117 provides average output current information,
enabling various applications requiring monitoring or control
of the output current.
30143280
FIGURE 14. Current Monitor
The average of CM output can be calculated by:
(14)
The current monitor output is only valid in continuous con-
duction operation. The current monitor has a limited band-
width of approximately one tenth of f
SW. Adding an R-C filter,
R
CM and CCM, on the output of current monitor with the cut off
frequency below one tenth of f
SW is recommended to attenu-
ate sampling noise.
Maximum Duty Cycle
When operating with a high PWM duty cycle, the high-side
NMOS device is forced off each cycle for 320ns to ensure that
C
HB is recharged and to allow time to sample and hold the
current in the low-side NMOS FET. This forced off-time limits
the maximum duty cycle of the controller. When designing a
regulator with high switching frequency and high duty cycle
requirements, a check should be made of the required maxi-
mum duty cycle against the graph shown in Figure 15. The
actual maximum duty cycle varies with the switching frequen-
cy as follows:
30143214
FIGURE 15. Maximum Duty Cycle vs Switching
Frequency
Thermal Protection
Internal thermal shutdown circuitry is provided to protect the
controller in the event the maximum junction temperature is
exceeded. When activated, typically at 165°C, the controller
is forced into a low power shutdown mode, disabling the out-
put drivers and the VCC regulator. This feature is designed to
prevent overheating and destroying the device.
17
www.national.com
LM5117
相关PDF资料 |
PDF描述 |
|---|---|
| LM604CMX | SPECIALTY ANALOG CIRCUIT, PDSO20 |
| LM604ACMX | SPECIALTY ANALOG CIRCUIT, PDSO20 |
| LM629M-6X | BRUSH DC MOTOR CONTROLLER, PDSO24 |
| LM629M-8X | BRUSH DC MOTOR CONTROLLER, PDSO24 |
| LM7005 | PLL FREQUENCY SYNTHESIZER, 35 MHz, PDIP24 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LM5117PMH/NOPB | 功能描述:DC/DC 开关控制器 RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| LM5117PMH/NOPB | 制造商:Texas Instruments 功能描述:IC DC-DC CONV 750kHz TSSOP-20 制造商:Texas Instruments 功能描述:IC, DC-DC CONV, 750kHz, TSSOP-20 |
| LM5117PMHE/NOPB | 功能描述:DC/DC 开关控制器 Wide Input Range Sync Buck Cntlr RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| LM5117PMHX/NOPB | 功能描述:DC/DC 开关控制器 RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| LM5117PSQ/NOPB | 功能描述:DC/DC 开关控制器 Wide Input Range Sync Buck Cntlr RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
发布紧急采购，3分钟左右您将得到回复。