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| 型号： | LM95241EB |
| 厂商： | National Semiconductor |
| 文件页数： | 14/29页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION LM95241 |
| 标准包装： | 1 |
| 系列： | PowerWise®, TruTherm® |
| 传感器类型： | 温度 |
| 传感范围： | 0°C ~ 140°C |
| 接口： | SMBus（2 线/I²C） |
| 灵敏度： | ±1°C |
| 电源电压： | 3 V ~ 3.6 V |
| 嵌入式： | 否 |
| 已供物品： | 板 |
| 已用 IC / 零件： | LM95241 |
| 相关产品： | LM95241CIMMX-ND - IC TEMP SENSOR DUAL REMOTE 8MSOP LM95241CIMMX-2-ND - IC TEMP SENSOR DUAL REMOTE 8MSOP LM95241CIMMX-1-ND - IC TEMP SENSOR DUAL REMOTE 8MSOP LM95241CIMM-2DKR-ND - IC TEMP SENS DUAL REM DIO 8-MSOP LM95241CIMM/NOPBDKR-ND - IC TEMP SENS DUAL REM DIO 8-MSOP LM95241CIMM-2CT-ND - IC TEMP SENS DUAL REM DIO 8-MSOP LM95241CIMM/NOPBCT-ND - IC TEMP SENS DUAL REM DIO 8-MSOP LM95241CIMM-2TR-ND - IC TEMP SENS DUAL REM DIO 8-MSOP LM95241CIMM/NOPBTR-ND - IC TEMP SENS DUAL REM DIO 8-MSOP LM95241CIMM-1DKR-ND - IC TEMP SENSOR REMOTE DL 8-MSOP 更多... |
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SNIS143E – AUGUST 2006 – REVISED MARCH 2013
1
9
1
9
SMBCLK
SMBDAT
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Start by
Master
Frame 1
Serial Bus Address Byte
Ack
by
LM95241
Frame 2
Data Byte from the LM95241
NoAck Stop
by by
Master Master
Figure 10. Serial Bus byte Read from a Register with the internal Command Register preset to desired
value.
1
9
1
9
SMBCLK
SMBDAT
A6
A5
A4
A3
A2
A1
A0 R/W
D7
D6
D5
D4
D3
D2
D1
D0
Start by
Master
Frame 1
Ack
by
LM95241
Frame 2
Ack Repeat
by Start by
LM95241 Master
Serial Bus Address Byte
Command Byte
SMBCLK
1
9
1
9
(Continued)
SMBDAT
(Continued)
A6
A5
A4
A3
A2
A1
A0 R/W
Ack
D7
D6
D5
D4
D3
D2
D1
D0
No Ack Stop
by
by
by
Frame 3
Serial Bus Address Byte
LM95241
Frame 4
Data Byte from the LM95241
Master Master
Figure 11. Serial Bus Write followed by a Repeat Start and Immediate Read
SERIAL INTERFACE RESET
In the event that the SMBus Master is RESET while the LM95241 is transmitting on the SMBDAT line, the
LM95241 must be returned to a known state in the communication protocol. This may be done in one of two
ways:
1. When SMBDAT is LOW, the LM95241 SMBus state machine resets to the SMBus idle state if either
SMBDAT or SMBCLK are held low for more than 35ms (t TIMEOUT ). Note that according to SMBus
specification 2.0 all devices are to timeout when either the SMBCLK or SMBDAT lines are held low for 25-
35ms. Therefore, to insure a timeout of all devices on the bus the SMBCLK or SMBDAT lines must be held
low for at least 35ms.
2. When SMBDAT is HIGH, have the master initiate an SMBus start. The LM95241 will respond properly to an
SMBus start condition at any point during the communication. After the start the LM95241 will expect an
SMBus Address address byte.
ONE-SHOT CONVERSION
The One-Shot register is used to initiate a single conversion and comparison cycle when the device is in standby
mode, after which the device returns to standby. This is not a data register and it is the write operation that
causes the one-shot conversion. The data written to this address is irrelevant and is not stored. A zero will
always be read from this register.
LM95241 Registers
Command register selects which registers will be read from or written to. Data for this register should be
transmitted during the Command Byte of the SMBus write communication.
14
Product Folder Links: LM95241
Copyright ? 2006–2013, Texas Instruments Incorporated
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