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参数资料
| 型号： | LM98725 |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO56 |
| 封装： | TSSOP-56 |
| 文件页数： | 3/14页 |
| 文件大小： | 464K |
| 代理商： | LM98725 |
AC Timing Specifications
The following specifications apply for VA = VD = VR = VC = 3.3V, C
L = 10pF, and fINCLK = 27MHz unless otherwise specified.
Boldface limits apply for T
A = TMIN to TMAX; all other limits T
A = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Input Clock Timing Specifications
f
INCLK
Input Clock Frequency
INCLK = PIXCLK
0.66
27 (Mode 3)
MHz
(Pixel Rate Clock)
1
30 (Mode 2)
1
30 (Mode 1)
INCLK = ADCCLK
2
81 (Mode 3)
MHz
(ADC Rate Clock)
60 (Mode 2)
30 (Mode 1)
T
dc
Input Clock Duty Cycle
40/60
50/50
60/40
%
Full Channel Latency Specifications
t
LAT3
3 Channel Mode Pipeline Delay
PIXPHASE0
24
T
ADC
PIXPHASE1
23 1/2
PIXPHASE2
23
PIXPHASE3
22 1/2
t
LAT2
2 Channel Mode Pipeline Delay
PIXPHASE0
21
T
ADC
PIXPHASE1
20 1/2
PIXPHASE2
20
PIXPHASE3
19 1/2
t
LAT1
1 Channel Mode Pipeline Delay
PIXPHASE0
19
T
ADC
PIXPHASE1
18 1/2
PIXPHASE2
18
PIXPHASE3
17 1/2
SH_R Timing Specifications
t
SHR_S
SH_R Setup Time
2
ns
t
SHR_H
SH_R Hold Time
2
ns
LVDS Output Timing Specifications
TX
pp0
TXCLK to Pulse Position 0
LVDS Output
-0.26
0
0.26
ns
TX
pp1
TXCLK to Pulse Position 1
Specifications not
1.50
1.76
2.02
ns
TX
pp2
TXCLK to Pulse Position 2
tested in production.
3.26
3.53
3.79
ns
TX
pp3
TXCLK to Pulse Position 3
Min/Max guaranteed
5.03
5.29
5.55
ns
TX
pp4
TXCLK to Pulse Position 4
by design,
6.80
7.06
7.32
ns
TX
pp5
TXCLK to Pulse Position 5
characterization and statistical
8.56
8.82
9.08
ns
TX
pp6
TXCLK to Pulse Position 6
analysis.
10.32
10.58
10.84
ns
CMOS Output Timing Specifications
t
CRDO
CLKOUT Rising Edge to CMOS
Output Data Transition
f
INCLK = 40MHz
2
4.5
9
ns
INCLK = ADCCLK
(ADC Rate Clock)
Serial Interface Timing Specifications
11
www.national.com
LM98725
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