参数资料
型号: LMK04002BEVAL
厂商: National Semiconductor
文件页数: 37/65页
文件大小: 0K
描述: BOARD EVAL PRECISION CLOCK PLL
标准包装: 1
系列: PowerWise®
主要目的: 计时,时钟调节器
嵌入式:
已用 IC / 零件: LMK04002
主要属性: 122.88 MHz VCXO
次要属性: 集成式 PLL 和 VCO
已供物品: 板,线缆
产品目录页面: 1275 (CN2011-ZH PDF)
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Register 15
PLL2_N: PLL2_N Counter
The PLL2_N Counter is 18 bits wide. It divides the output of the VCO Divider and is connected to the PLL2
Phase Detector. Each time the PLL2_N Counter value is updated via the uWire interface, an internal algorithm is
triggered that optimizes the VCO performance.
Table 30. PLL2_N: PLL2_N Counter Values
N [17:0]
VALUE
b17
b16
...
b6
b5
b4
b3
b2
b1
b0
0
...
0
Not Valid
0
1
0
1
0
2
.
...
1
262143
PLL2_CP_GAIN: PLL2 Charge Pump Current and Output Control
The PLL2 charge pump output current level is controlled with the PLL2_CP_GAIN register. The following table
presents the charge pump current control values.
Table 31. PLL2_CP_GAIN: PLL2 Charge Pump Current Selections
PLL2_CP_GAIN [1:0]
CP_TRI
Charge Pump Current (A)
b1
b0
X
1
Hi-Z
0
100
0
1
0
400
1
0
1600
1
0
3200
VCO_DIV: PLL2 VCO Divide Register
A divider is provided on the output of the PLL2 VCO to enable a wide range of output clock frequencies. The
output of this divider is placed on the input path for the clock distribution section, which feeds each of the
individual clock channels. The divider provides integer divide ratios from 2 to 8.
Table 32. VCO_DIV: PLL2 VCO Divider Values
VCO_DIV [3:0]
Divide Value
b3
b2
b1
b0
0
Invalid
0
1
Invalid
0
1
0
2
0
1
3
0
1
0
4
0
1
0
1
5
0
1
0
6
0
1
7
1
0
8
42
Copyright 2008–2011, Texas Instruments Incorporated
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