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参数资料
| 型号： | LMK04002BISQE/NOPB |
| 厂商： | National Semiconductor |
| 文件页数： | 28/65页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK COND 1.6GHZ W/PLL 48LLP |
| 标准包装： | 1 |
| 系列： | PowerWise® |
| 类型： | 时钟调节器 |
| PLL： | 是 |
| 输入： | LVCMOS |
| 输出： | LVCMOS，2VPECL，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:7 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.75GHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-LLP（7x7） |
| 包装： | 标准包装 |
| 产品目录页面： | 1275 (CN2011-ZH PDF) |
| 其它名称： | LMK04002BISQEDKR |
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N
R
X FOSCin
(VCO_DIV CLK_DIV)
FCLK error =
N
R
FOSCin
(VCO_DIV CLK_DIV)
FCLK =
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
CLKoutX_MUX: Clock Output Mux
The output of each CLKoutX channel pair is controlled by its' channel multiplexer (mux). The mux can select
between several signals: bypassed, divided only, divided and delayed, or delayed only.
Table 10. CLKoutX_MUX: Clock Channel Multiplexer Control Bits
CLKout_MUX [1:0]
Clock Mode
b1
b0
0
Bypassed
0
1
Divided
1
0
Delayed
1
Divided and Delayed
Registers 5, 6
These registers are reserved. These register values should not be modified from the values shown in the register
map.
Register 7
Reset bit
This bit is only in register R7. The use of this bit is optional and it should be set to '0' if not used. Setting this bit
to a '1' forces all registers to their power on reset condition and therefore automatically clears this bit.
Registers 8, 9
These registers are reserved. These register values should not be modified from the values shown in the register
map.
Register 10
RC_DLD1_Start: PLL1 Digital Lock Detect Run Control bit
This bit is used to control the state machine for the PLL2 VCO tuning algorithm. The following table describes the
function of this bit.
Table 11. RC_DLD1_Start bit States
RC_DLD1_Start
Description
1
The PLL2 VCO tuning algorithm trigger is delayed until PLL1 Digital Lock Detect is valid.
0
The PLL2 VCO tuning algorithm runs immediately after any PLL2_N counter update, despite the state of PLL1
Digital Lock Detect.
If the user is unsure of the state of the reference clock input at startup of the LMK040xx device, setting
RC_DLD1_Start = 0 will allow PLL2 to tune and lock the internal VCO to the oscillator attached to the OSCin
port. This ensures that the active clock outputs will start up at frequencies close to their desired values. The error
in clock output frequency will depend on the open loop accuracy of the oscillator driving the OSCin port. The
frequency of an active clock output is normally given by:
If the open loop frequency accuracy of the external oscillator (either a VCXO or crystal based oscillator) is "X"
ppm, then the error in the output clock frequency (FCLK error) will be:
34
Copyright 2008–2011, Texas Instruments Incorporated
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LMK04002BISQX | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
| LMK04002BISQX/NOPB | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| LMK04010BISQ | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
| LMK04010BISQ/NOPB | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| LMK04010BISQE | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
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