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| 型号： | LMP90078MHX/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封装： | LEAD FREE, PLASTIC, MO-153, TSSOP-28 |
| 文件页数： | 21/62页 |
| 文件大小： | 1721K |
| 代理商： | LMP90078MHX/NOPB |
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calibration coefficients to the output codes to minimize
the LMP900xx’s offset and gain errors.
The last known offset or gain calibration coefficients can
come from two sources. The first source is the default
coefficient which is pre-determined and burnt in the
device’s non-volatile memory. The second source is from
a previous calibration run of Type 1: Correction.
The benefits of using type 2 calibration is a higher throughput,
lower power consumption, and slightly better noise. The exact
savings would depend on the number of channels being
scanned, and the ODR and gain of each channel.
Using Background Calibration:
There are four modes of background calibration, which can
be programmed using the BGCALCN bits. They are as fol-
lows:
1.
BgcalMode0: Background Calibration OFF
2.
BgcalMode1: Offset Correction / Gain Estimation
3.
BgcalMode2: Offset Correction / Gain Correction
Follow Figure 13 to set other appropriate registers when
using this mode.
4.
BgcalMode3: Offset Estimation / Gain Estimation
30169730
FIGURE 13. BgcalMode2 Register Settings
If operating in BgcalMode2, four channels (with the same
ODR) are being converted, and FGA_BGCAL = 0 (default),
then the ODR is reduced by:
1.
0.19% of 1.6775 SPS
2.
0.39% of 3.355 SPS
3.
0.78% of 6.71 SPS
4.
1.54% of 13.42 SPS
5.
3.03% of 26.83125 SPS
6.
5.88% of 53.6625 SPS
7.
11.11% of 107.325 SPS
8.
20% of 214.65 SPS
16.2.2 System Calibration
The LMP900xx provides some unique features to support
easy system offset and system gain calibrations.
The System Calibration Offset Registers (CHx_SCAL_OFF-
SET) hold the System Calibration Offset Coefficients in 16-
bit, two's complement binary format. The System Calibration
Gain Registers (CHx_SCAL_GAIN) hold the System Calibra-
tion Gain Coefficient in 16-bit, 1.15, unsigned, fixed-point
binary format. For each channel, the System Calibration Off-
set coefficient is subtracted from the conversion result prior
to the division by the System Calibration Gain coefficient.
A data-flow diagram of these coefficients can be seen in Fig-
30169731
FIGURE 14. System Calibration Data-Flow Diagram
There are four distinct sets of System Calibration Offset and
System Calibration Gain Registers for use with CH0-CH3.
CH4-CH6 reuse the registers of CH0-CH2, respectively.
The LMP900xx provides two system calibration modes that
automatically fill the Offset and Gain coefficients for each
channel. These modes are the System Calibration Offset Co-
efficient Determination mode and the System Calibration
Gain Coefficient Determination mode. The System Calibra-
tion Offset Coefficient Determination mode must be entered
prior to the System Calibration Gain Coefficient Determina-
tion mode, for each channel.
The system zero-scale condition is a system input condition
(sensor loading) for which zero (0x0000) system-calibrated
output code is desired. It may not, however, cause a zero in-
put voltage at the input of the ADC.
The system reference-scale condition is usually the system
full-scale condition in which the system's input (or sensor's
loading) would be full-scale and the desired system-calibrat-
ed output code would be 0x8000 (unsigned 16-bit binary).
However, system full-scale condition need not cause full-
scale input voltage at the input of the ADC.
The system reference-scale condition is not restricted to just
the system full-scale condition. In fact, it can be any arbitrary
fraction of full-scale (up to 1.25 times) and the desired system-
calibrated output code can be any appropriate value (up to
0xA000). The CHx_SCAL_GAIN register must be written with
the desired system-calibrated output code (default:0x8000)
before entering the System Calibration Gain Coefficient De-
termination mode. This helps in in-place system calibration.
Below are the detailed procedures for using the System Cal-
ibration Offset Coefficient Determination and System Cali-
bration Gain Coefficient Determination modes.
System Calibration Offset Coefficient Determination
mode
1.
Apply system zero-scale condition to the channel (CH0/
CH1/CH2/CH3).
2.
Enter the System Calibration Offset Coefficient
Determination mode by programming 0x1 in the
SCALCN register.
3.
LMP900xx starts a fresh conversion at the selected
output data rate for the selected channel. At the end of
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LMP90080/LMP90079/LMP90078/LMP90077
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LMP90079 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Sensor AFE System: Multi-Channel, Low-Power 16-Bit |
| LMP90079MH/NOPB | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| LMP90079MHE/NOPB | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| LMP90079MHX/NOPB | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| LMP90080 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Sensor AFE System: Multi-Channel, Low-Power 16-Bit |
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