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参数资料
| 型号： | LMX2324TM/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO16 |
| 封装： | TSSOP-16 |
| 文件页数： | 11/14页 |
| 文件大小： | 183K |
| 代理商： | LMX2324TM/NOPB |
2.0 Programming Description
2.1 MICROWIRE INTERFACE
The LMX2324 register set can be accessed through the MICROWIRE interface. A 18-bit shift register is used as a temporary
register to indirectly program the on-chip registers. The shift register consists of a 17-bit DATA[16:0] field and a 1-bit address
(ADDR) field as shown below. The address field is used to decode the internal register address. Data is clocked into the shift
register in the direction from MSB to LSB, when the CLOCK signal goes high. On the rising edge of Load Enable (LE) signal, data
stored in the shift register is loaded into the addressed latch.
MSB
LSB
DATA[16:0]
ADDR
17
1
0
2.1.1 Registers’ Address Map
When Load Enable (LE) is transitioned high, data is transferred from the 18-bit shift register into the appropriate latch depending
on the state of the ADDRESS bit. A multiplexing circuit decodes the address bit and writes the data field to the corresponding
internal register.
REGISTER
ADDRESSED
ADDRESS BIT
ADDR
R Register
1
N Register
0
LMX2324
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