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参数资料
| 型号： | LMX2335USLB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, PQCC16 |
| 封装： | PLASTIC, CSP-16 |
| 文件页数： | 6/20页 |
| 文件大小： | 379K |
| 代理商： | LMX2335USLB |
Application Information
A block diagram of the basic phase locked loop is shown in
Figure 1.
Loop Gain Equations
A linear control system model of the phase feedback for a
PLL in the locked state is shown in
Figure 2. The open loop
gain is the product of the phase comparator gain (Kφ), the
VCO gain (K
VCO/s), and the loop filter gain Z(s) divided by
the gain of the feedback counter modulus (N). The passive
loop filter configuration used is displayed in
Figure 3, WHILE
the complex impedance of the filter is given in equation 2.
(1)
(2)
The time constants which determine the pole and zero fre-
quencies of the filter transfer function can be defined as
(3)
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency,
ω, the filter time contants T1 and T2, and
the design constants K
φ,K
VCO, and N.
(4)
From
Equation (3) we can see that the phase term will be
dependent on the single pole and zero such that the phase
margin is determined in
Equation (1).
φ(ω) = tan1 (ω T2) tan1 (ω T1) + 180C
(5)
A plot of the magnitude and phase of G(s) H(s) for a stable
loop, is shown in
Equation (4) with a solid trace. The param-
eter
φ
p shows the amount of phase margin that exists at the
point the gain drops below zero (the cutoff frequency wp of
the loop). In a critically damped system, the amount of phase
margin would be approximately 45 degrees.
If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop band-
width, wp, the loop response time would be approximately
halved. Because the filter attenuation at the comparison
frequency also diminishes, the spurs would have increased
by approximately 6 dB. In the proposed Fastlock scheme,
the higher spur levels and wider loop filter conditions would
exist only during the initial lock-on phase — just long enough
to reap the benefits of locking faster. The objective would be
to open up the loop bandwidth but not introduce any addi-
tional complications or compromises related to our original
design criteria. We would ideally like to momentarily shift the
curve
Figure 4 over to a different cutoff frequency, illustrated
by dotted line, without affecting the relative open loop gain
and phase relationships. To maintain the same gain/phase
relationship at twice the original cutoff frequency, other terms
in the gain and phase equations 4 and 5 will have to com-
pensate by the corresponding “1/w” or “1/w
2” factor. Exami-
nation of equations 3 and 5 indicates the damping resistor
variable R2 could be chosen to compensate with “w” terms
for the phase margin. This implies that another resistor of
equal value to R2 will need to be switched in parallel with R2
during the initial lock period. We must also insure that the
magnitude of the open loop gain, H(s)G(s) is equal to zero at
wp’ = 2 wp. K
VCO,Kφ, N, or the net product of these terms
can be changed by a factor of 4, to counteract with w
2 term
present in the denominator of equation 3. The K
φ term was
chosen to complete the transformation because it can
readily be switched between 1X and 4X values. This is
accomplished by increasing the charge pump output current
from 1 mA in the standard mode to 4 mA in Fastlock.
DS101367-13
FIGURE 1. Conventional PLL Architecture
DS101367-14
FIGURE 2. PLL Linear Model
DS101367-15
FIGURE 3. Passive Loop Filter
LMX2335U/LMX2336U
www.national.com
14
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相关代理商/技术参数 |
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|---|---|
| LMX2335USLBX | 功能描述:IC FREQ SYNTH DUAL 16LAMINATECSP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:PLLatinum™ 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| LMX2335UTM | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2335UTM/NOPB | 功能描述:IC FREQ SYNTHESIZER DUAL 16TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:PLLatinum™ 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| LMX2335UTMX | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2336 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications |
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