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参数资料
| 型号： | LMX2335USLBX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | XO, clock |
| 英文描述： | PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, PQCC16 |
| 封装： | PLASTIC, CSP-16 |
| 文件页数： | 29/48页 |
| 文件大小： | 3127K |
| 代理商： | LMX2335USLBX |
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Test Setups
(Continued)
LMX2335U and LMX2336U f
IN
Sensitivity Test Setup
10136740
The block diagram above illustrates the setup required to
measure the LMX2336U device’s RF1 input sensitivity level.
The
same
setup
is
used
LMX2336SLEEB Evaluation Boards. The RF2 input sensitiv-
ity test setup is similar to the RF1 sensitivity test setup. The
purpose of this test is to measure the acceptable signal level
to the f
RF1 input of the PLL chip. Outside the acceptable
signal range, the feedback divider begins to divide incor-
rectly and miscount the frequency.
The setup uses an open loop configuration. A power supply
is connected to V
cc
and the bias voltage is swept from 2.7V
to 5.5V. The RF2 PLL is powered down (PWDN RF2 Bit = 1).
By means of a signal generator, an RF signal is applied to
the f
IN
RF1 pin. The 3 dB pad provides a 50
match
between the PLL and the signal generator. The OSC
in
pin is
tied to V
. The N value is typically set to 10000 in Code
Loader, i.e. RF1 N_CNTRB Word = 156 and RF1 N_CNTRA
Word = 16 for PRE RF1 Bit = 0. The feedback divider output
is routed to the F
o
LD pin by selecting the
RF1 PLL N Divider
Output
word (F
LD Word = 6 or 14) in Code Loader. A
Universal Counter is connected to the F
o
LD pin and tied to
for
the
LMX2336TMEB/
the 10 MHz reference output of the signal generator. The
output of the feedback divider is thus monitored and should
be equal to f
IN
RF1 / N.
The f
RF1 input frequency and power level are then swept
with the signal generator. The measurements are repeated
at different temperatures, namely T
= -40C, +25C, and
+85C. Sensitivity is reached when the frequency error of the
divided RF input is greater than or equal to 1 Hz. The power
attenuation from the cable and the 3 dB pad must be ac-
counted for. The feedback divider will actually miscount if too
much or too little power is applied to the f
IN
RF1 input.
Therefore, the allowed input power level will be bounded by
the upper and lower sensitivity limits. In a typical application,
if the power level to the f
IN
RF1 input approaches the sen-
sitivity limits, this can introduce spurs and degradation in
phase noise. When the power level gets even closer to these
limits, or exceeds it, then the RF1 PLL loses lock.
The LMX2335U f
sensitivity test setup is very much similar
to the above test setup.
L
www.national.com
29
相关PDF资料 |
PDF描述 |
|---|---|
| LMX2335UTM | PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2335U | PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2336 | PLLatinum⑩ Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2336LSLB | PLLatinum⑩ Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2336LTM | PLLatinum⑩ Low Power Dual Frequency Synthesizer for RF Personal Communications |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LMX2335UTM | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2335UTM/NOPB | 功能描述:IC FREQ SYNTHESIZER DUAL 16TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:PLLatinum™ 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| LMX2335UTMX | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2336 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications |
| LMX2336 WAF | 制造商:Texas Instruments 功能描述: |
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