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参数资料
| 型号： | LMX2350TM/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO24 |
| 封装： | PLASTIC, TSSOP-24 |
| 文件页数： | 6/21页 |
| 文件大小： | 405K |
| 代理商： | LMX2350TM/NOPB |
Programming Description (Continued)
3.2.1 (RF_R [22 - 23] )
DLL_MODE
V2_EN
BIT
LOCATION
FUNCTION
0
1
DLL_MODE
RF_R [23]
Delay Line Loop Calibration
Mode
Slow
Fast
V2_EN
RF_R [22]
RF_Voltage Doubler Enable
Disabled
Enabled
1. V2_EN bit when set high enables the voltage doubler for the RF Charge Pump supply.
2. DLL_MODE bit should be set to one for normal usage.
3.2.2 RF_CP_WORD
(RF_R[17]-[21])
CP_8X
CP_4X
CP_2X
CP_1X
RF_PD_POL
RF_PD_POL ( RF_R[17] ) should be set to one when RF VCO characteristics are positive. When RF VCO frequency decreases
with increasing control voltage RF_PD_POL should be set to zero.
CP_1x, CP_2x, CP_4x, and CP_8x are used to step the RF Charge Pump output current magnitude from 100 uA to 1.6 mA in
100uA steps as shown in the table below.
RF Charge Pump Output Truth Table
ICPo uA (typ)
CP8x
CP4x
CP2x
CP1x
RF_R[21]
RF_R[20]
RF_R[19]
RF_R[18]
100
0000
200
0001
300
0010
400
0011
-
----
900
1000
-
----
1600
1111
4.0 PROGRAMMABLE DIVIDERS (N COUNTERS)
4.1 IF_N Register
If the Control Bits (CTL [1:0]) are 01, data is transferred from the 24-bit shift register into the IF_N register latch which sets the
PLL 15 bit programmable N counter value and various control functions. The IF_N counter consists of the 3-bit swallow counter
(A counter), and the 12 bit programmable counter (B counter). Serial data format is shown below in tables 4.1.2 and 4.1.3. The
divide ratio (IF_NB_CNTR) must be
≥3. The divide ratio is programmed using the bits IF_N_CNTR as shown in tables 4.1.2 and
4.1.3. The divide ratio must be
≥56. The CMOS [3:0] bits program the 2 CMOS outputs detailed in section 4.4.
MSB
LSB
IF_CTL_WORD [2:0]
CMOS [3:0]
IF_NB_CNTR [11:0]
IF_NA_CNTR [2:0]
0
1
23
21
20
17
16
5
4
2
1
0
4.1.1 IF_CTL_WORD
(IF_R[21]-[23])
MSB
LSB
IF_CNT_RST
PWDN_IF
PWDN_MODE
Note: See section 4.2.1.2 for IF control word truth table.
LMX2350/LMX2352
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| LMX2350TMX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Serial-Input Frequency Synthesizer |
| LMX2350TMX/NOPB | 功能描述:IC FREQ SYNTH LOPWR DUAL 24TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:PLLatinum™ 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| LMX2352 | 制造商:未知厂家 制造商全称:未知厂家 功能描述: |
| LMX2352SLBX | 功能描述:IC FREQ SYNTH DUAL 24LAMINATECSP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:PLLatinum™ 标准包装:39 系列:- 类型:* PLL:带旁路 输入:时钟 输出:时钟 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 频率 - 最大:170MHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:* 封装/外壳:* 供应商设备封装:* 包装:* |
| LMX2352TM | 制造商:Texas Instruments 功能描述:IC, DUAL FREQ SYNTHESIZER 1.2GHZ 24-TSSOP, PLL Type:Frequency Synthesis, Frequen |
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