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参数资料
| 型号： | LP3918TLX-I |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PBGA25 |
| 封装： | 2.50 X 2.50 MM, MICRO, SMD-25 |
| 文件页数： | 19/30页 |
| 文件大小： | 1271K |
| 代理商： | LP3918TLX-I |
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20211613
FIGURE 6. Bit Transfer
Each data transaction is composed of a Start Condition, a
number of byte transfers (set by the software) and a Stop
Condition to terminate the transaction. Every byte written to
the SDA bus must be 8 bits long and is transferred with the
most significant bit first. After each byte, an Acknowledge sig-
nal must follow. The following sections provide further details
of this process.
START AND STOP
The Master device on the bus always generates the Start and
Stop Conditions (control codes). After a Start Condition is
generated, the bus is considered busy and it retains this sta-
tus until a certain time after a Stop Condition is generated. A
high-to-low transition of the data line (SDA) while the clock
(SCL) is high indicates a Start Condition. A low-to-high tran-
sition of the SDA line while the SCL is high indicates a Stop
Condition.
20211610
FIGURE 7. Start and Stop Conditions
In addition to the first Start Condition, a repeated Start Con-
dition can be generated in the middle of a transaction. This
allows another device to be accessed, or a register read cycle.
ACKNOWLEDGE CYCLE
The Acknowledge Cycle consists of two signals: the acknowl-
edge clock pulse the master sends with each byte transferred,
and the acknowledge signal sent by the receiving device.
The master generates the acknowledge clock pulse on the
ninth clock pulse of the byte transfer. The transmitter releases
the SDA line (permits it to go high) to allow the receiver to
send the acknowledge signal. The receiver must pull down
the SDA line during the acknowledge clock pulse and ensure
that SDA remains low during the high period of the clock
pulse, thus signaling the correct reception of the last data byte
and its readiness to receive the next byte.
20211628
FIGURE 8. Bus Acknowledge Cycle
“ACKNOWLEDGE AFTER EVERY BYTE” RULE
The master generates an acknowledge clock pulse after each
byte transfer. The receiver sends an acknowledge signal after
every byte received.
There is one exception to the “acknowledge after every byte”
rule.
When the master is the receiver, it must indicate to the trans-
mitter an end of data by not-acknowledging (“negative ac-
knowledge”) the last byte clocked out of the slave. This
“negative acknowledge” still includes the acknowledge clock
pulse (generated by the master), but the SDA line is not pulled
down.
ADDRESSING TRANSFER FORMATS
Each device on the bus has a unique slave address. The
LP3918 operates as a slave device with the address 7h’7E
(binary 1111110). Before any data is transmitted, the master
transmits the address of the slave being addressed. The slave
device should send an acknowledge signal on the SDA line,
once it recognizes its address.
The slave address is the first seven bits after a Start Condi-
tion. The direction of the data transfer (R/W) depends on the
bit sent after the slave address — the eighth bit.
When the slave address is sent, each device in the system
compares this slave address with its own. If there is a match,
the device considers itself addressed and sends an acknowl-
edge signal. Depending upon the state of the R/W bit (1:read,
0:write), the device acts as a transmitter or a receiver.
CONTROL REGISTER WRITE CYCLE
Master device generates start condition.
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LP3918
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相关代理商/技术参数 |
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| LP3918TLX-L | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Battery Charge Management and Regulator Unit |
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| LP3919RL-B/NOPB | 功能描述:PMIC 解决方案 RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| LP3919RL-C/NOPB | 功能描述:PMIC 解决方案 RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
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