参数资料
型号: LP3946ILD
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 电源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO14
文件页数: 6/15页
文件大小: 337K
代理商: LP3946ILD
Application Notes (Continued)
THERMAL PERFORMANCE OF LLP PACKAGE
The LP3945 and LP3946 are monolithic devices with inte-
grated pass transistors. To enhance the power dissipation
performance, the Leadless Lead frame Package, or LLP, is
used. The LLP package is designed for improved thermal
performance because of the exposed die attach pad at the
bottom center of the package. It brings advantage to thermal
performance by creating a very direct path for thermal dissi-
pation. Compared to the traditional leaded packages where
the die attach pad is embedded inside the mold compound,
the LLP reduces a layer of thermal path.
The thermal advantage of the LLP package is fully realized
only when the exposed die attach pad is soldered down to a
thermal land on the PCB board and thermal vias are planted
underneath the thermal land. Based on a LLP thermal mea-
surement, junction to ambient thermal resistance (
θ
JA) can
be improved by as much as two times if a LLP is soldered on
the board with thermal land and thermal vias than if not.
An example of how to calculate for LLP thermal performance
is shown below:
By substituting 37C/W for
θ
JA, 125C for TJ and 70C for TA,
the maximum power dissipation allowed from the chip is
1.48W at T
A = 70C. If VCHG-IN is at 5.0V and a 3.0V battery
is being charged, then 740 mA of I
CHG can safely charge the
battery. More power can be safely dissipated at ambient
temperatures below 70C. Less power can be safely dissi-
pated at ambient temperatures above 70C. The maximum
power dissipation for operation can be increased by 27 mW
for each degree below 70C, and it must be de-rated by 27
mW for each degree above 70C.
LAYOUT CONSIDERATION
The LP3945 and LP3946 have exposed die attach pad
located at the bottom center of the LLP package. It is im-
perative to create a thermal land on the PCB board when
designing a PCB layout for the LLP package. The thermal
land helps to conduct heat away from the die, and the land
should be the same dimension as the exposed pad on the
bottom of the LLP (1:1 ratio). In addition, thermal vias should
be added inside the thermal land to conduct more heat away
from the surface of the PCB to the ground plane. Typical
pitch and outer diameter for these thermal vias are 1.27 mm
and 0.33 mm respectively. Typical copper via barrel plating is
1 oz. although thicker copper may be used to improve ther-
mal performance. The LP3945 and LP3946 bottom pad is
connected to ground. Therefore, the thermal land and vias
on the PCB board need to be connected to ground.
For more information on board layout techniques, refer to
Application Note 1187 “Leadless Leadframe Package
(LLP)”. The application note also discuss package handling,
solder stencil, and assembly.
LP3945 AND LP3946 EVALUATION BOARDS
The LP3945 and LP3946 evaluation boards and instruction
manuals are available for order on National’s website
(www.national.com). The LP3945 evaluation board has on-
board I
2C interface capability for more flexibility. Please visit
National’s website for more detail.
20066518
w = write (sda = “0”)
r = read (sda = “1”)
ack = acknowledge (sda pulled down by either master or slave)
rs = repeated start
FIGURE 8. LP3945 (Slave) Register Read
LP3945/LP3946
www.national.com
14
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PDF描述
LP3972SQXA413 1-CHANNEL POWER SUPPLY SUPPORT CKT, QCC40
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LP3972SQ-5810 1-CHANNEL POWER SUPPLY SUPPORT CKT, QCC40
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