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| 型号： | LP5521YQX/NOPB |
| 厂商： | National Semiconductor |
| 文件页数： | 16/44页 |
| 文件大小： | 0K |
| 描述： | IC LED DRIVER RGB 24-LLP |
| 标准包装： | 4,500 |
| 系列： | PowerWise® |
| 恒定电流： | 是 |
| 拓扑： | PWM，切换式电容器（充电泵） |
| 输出数： | 3 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光，照明管理装置（LMU） |
| 类型 - 次要： | RGB |
| 频率： | 1.25MHz |
| 电源电压： | 2.7 V ~ 5.5 V |
| 输出电压： | 4.55V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 供应商设备封装： | 24-LLP |
| 包装： | 带卷 (TR) |
| 工作温度： | -30°C ~ 85°C |
| 其它名称： | LP5521YQX |
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SNVS441F – JANUARY 2007 – REVISED FEBRUAY 2013
LED CONTROLLER OPERATION MODES
Operation modes are defined in register address 01H. Each output channel (R, G, B) operation mode can be
configured separately. MODE registers are synchronized to 32 kHz clock. Delay between consecutive I 2 C writes
to OP_MODE register (01H) need to be longer than 153 μs (typ).
Table 6. OP_MODE register (01H):
Name
R_MODE
G_MODE
B_MODE
Bit
5:4
3:2
1:0
Description
R channel operation mode
00b = Disabled, reset R channel PC
01b = Load program to SRAM, reset R channel PC
10b = Run program defined by R_EXEC
11b = Direct control, reset R channel PC
G channel operation mode
00b = Disabled, reset G channel PC
01b = Load program to SRAM, reset G channel PC
10b = Run program defined by G_EXEC
11b = Direct control, reset G channel PC
B channel operation mode
00b = Disabled, reset B channel PC
01b = Load program to SRAM, reset B channel PC
10b = Run program defined by B_EXEC
11b = Direct control, reset B channel PC
DISABLED
Each channel can be configured to disabled mode. LED output current will be 0 during this mode. Disabled mode
resets respective channel’s PC.
LOAD Program
LP5521 can store 16 commands for each channel (R, G, B). Each command consists of 16 bits. Because one
register has only 8 bits, one command requires two I 2 C register addresses. In order to reduce program load time
LP5521 supports address auto incrementation. Register address is incremented after each 8 data bits. Whole
program memory can be written in one I 2 C write sequence.
Program memory is defined in the LP5521 register table, 10H to 2FH for R channel, 30H to 4FH for G channel
and 50H to 6FH for B channel. In order to be able to access program memory at least one channel operation
mode needs to be LOAD Program.
Memory writes are allowed only to the channel in LOAD mode. All channels are in hold while one or several
channels are in LOAD program mode, and PWM values are frozen for the channels which are not in LOAD
mode. Program execution continues when all channels are out of LOAD program mode. LOAD Program mode
resets respective channel’s PC.
RUN PROGRAM
RUN Program mode executes the commands defined in program memory for respective channel (R, G, B).
Execution register bits in ENABLE register define how program is executed. Program start position can be
programmed to Program Counter register (see the following tables). By manually selecting the PC start value,
user can write different lighting sequences to the memory, and select appropriate sequence with the PC register.
If program counter runs to end (15) the next command will be executed from program location 0.
If internal clock is used in the RUN program mode, operation mode needs to be written disabled (00b) before
disabling the chip (with CHIP_EN bit or EN pin) to ensure that the sequence starts from the correct program
counter (PC) value when restarting the sequence.
PC registers are synchronized to 32 kHz clock. Delay between consecutive I 2 C writes to PC registers (09H, 0AH,
0BH) need to be longer than 153 μs (typ.).
Note that entering LOAD program or Direct Control Mode from RUN PROGRAM mode is not allowed. Engine
execution mode should be set to Hold, and Operation Mode to disabled, when changing operation mode from
RUN mode.
16
Product Folder Links: LP5521
Copyright ? 2007–2013, Texas Instruments Incorporated
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