参数资料
型号: LPC11C24FBD48/301,
厂商: NXP Semiconductors
文件页数: 19/52页
文件大小: 0K
描述: IC MCU 32BIT 32KB FLASH 48LQFP
产品培训模块: Code Density for LPC11xx
特色产品: 32-bit ARM Cortex-M0 Microcontrollers
标准包装: 250
系列: LPC11Cxx
核心处理器: ARM? Cortex?-M0
芯体尺寸: 32-位
速度: 50MHz
连通性: CAN,CAN,I²C,Microwire,SPI,SSI,SSP,UART/USART
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 36
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 8K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-LQFP
包装: 托盘
其它名称: 568-6644
LPC11C24FBD48/301
26
Features
204 MHz dual-core architecture
- ARM Cortex-M4 core with hardware floating-point unit
- ARM Cortex-M0 asymmetrical coprocessor
Up to 1 MB dual-bank Flash, up to 264 KB SRAM, up to 4 KB EEPROM
LCD controller with display resolution up to 1024 x 768 pixels
10/100T Ethernet MAC with MII and RMII interfaces
Two HS USB 2.0 interfaces, with on-chip HS PHY
External memory controller
Memory protection unit
Innovative Quad SPI Flash interface (SPIFI)
State-configurable timer (SCT) subsystem
AES decryption with 128-bit secure OTP memories for key storage
Four reduced-power modes: sleep, deep-sleep, power-down, deep
power-down
Up to 164 GPIO, with configurable serial GPIO (SGPIO)
Pin compatibility with Cortex-M3 LPC1800 series
Flash
Up to 1 MB
Dual Bank
SRAM
Up to 264 KB
ROM
ROM /OTP
Bus System
ARM CORTEX-M4
Up to 204 MHz
ARM
Cortex-M0
Up to 204 MHz
Floating Point Unit
4 x UART
3 x SSP/SPI
2 x I2C
2 x I2S
SPI Flash
Interface
SDIO
External
Mem Ctrl
State Config
Timer
Serial
GPIO
4 x 32-bit
Timers
RTC
Alarm
Timer
MPU
NVIC
IPC
WIC
Debug
Trace
Motor Ctrl
PWM
Quad Enc
Interface
SYSTEM
SECURITY
MEMORY
CORE
SUBSYSTEM
OTP Key
Storage
2 x 8 Ch
10-bit ADC
10-bit
DAC
AES
Decryption
Brownout
Detector
GPDMA
Audio PLL
USB PLL
CPU PLL
IRC
Power-on
Reset
Watchdog
Timer
INTERFACES
TIMERS
ANALOG
2 x HS
USB 2.0
Ethernet
MAC
2 x CAN 2.0B
LCD
Controller
LPC4300 series
In the LPC4300 series, the Cortex-M4 processor
combines the benefits of a microcontroller with
high-performance digital signal processing features
such as single-cycle MAC, Single Instruction
Multiple Data (SIMD) techniques, saturating arithmetic, and a floating
point unit. The Cortex-M0 coprocessor off-loads many of the data
movement and I/O handling duties that can drain the bandwidth of
the Cortex-M4 core. The 256-bit-wide Flash memory architecture
reduces power consumption, by minimizing fetches, and maximizes
the performance of the core processor. The LPC4300 series is pin-for-
pin compatible with the LPC1800 Cortex-M3 series.
LPC4300 block diagram
4. LPC4300: World’s first dual-core DSCs
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