参数资料
型号: LPC11C24FBD48/301,
厂商: NXP Semiconductors
文件页数: 28/52页
文件大小: 0K
描述: IC MCU 32BIT 32KB FLASH 48LQFP
产品培训模块: Code Density for LPC11xx
特色产品: 32-bit ARM Cortex-M0 Microcontrollers
标准包装: 250
系列: LPC11Cxx
核心处理器: ARM? Cortex?-M0
芯体尺寸: 32-位
速度: 50MHz
连通性: CAN,CAN,I²C,Microwire,SPI,SSI,SSP,UART/USART
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 36
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 8K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-LQFP
包装: 托盘
其它名称: 568-6644
LPC11C24FBD48/301
34
5.
I2C Fm+ & smart-card / USART interfaces
I2C Fast-mode Plus (Fm+) interface
The simple, two-wire format of the Inter-Integrated Circuit (I2C) bus gives
designers a quick, easy way to extend core functionality and add new
features while saving power and minimizing the PCB footprint. Invented
by Philips (the founder of NXP) more than 30 years ago, the I2C bus is now
a de facto worldwide standard. The Fast-mode Plus version supports
speeds up to 1 Mbit/s, and offers a sink capability that can be used to
support higher currents or longer distances.
Features
Supports 400 kbit/s Fast-mode (Fm) and 1 Mbit/s Fast-mode Plus (Fm+)
Easy to configure as master, slave, or master/slave
Programmable clocks enable versatile rate control
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without
corruption of serial data on the bus
Serial clock synchronization lets devices with different bit rates
communicate via one serial bus
Serial clock synchronization enables handshake mechanism to
suspend/resume serial transfer
Supports multiple address recognition and a bus monitor mode
Provides open-drain I/O pins conforming to the full specification
I2C interface selection guide
Series
ARM core
Memory
I2C controller
Flash (KB)
SRAM (KB)
Fm
Fm+
LPC1300
Cortex-M3
Up to 32
8
-
Up to 1
LPC1700
Cortex-M3
Up to 512
Up to 96
Up to 2
Up to 1
LPC1800
Cortex-M3
Up to 1024
(2 x 512)
Up to 200
Up to 1
LPC4300
Cortex-M4
Up to 1024
(2 x 512)
Up to 264
Up to 1
Smart-card interface (USART)
To support a wide range of communication interfaces, NXP integrates a
full-featured Universal Synchronous/Asynchronous Receiver/Transmitter
(USART). The USART can operate as a standard asynchronous-only
UART, or interface with a smart-card or infrared (IrDA) device. By
including a fractional baud-rate generator, the USART supports
standard baud rates with any clock frequency above 2 MHz, and thus
eliminates the need for value-specific crystals.
Features
Smart-card mode conforms to ISO7816 specification
Auto-baud capabilities and FIFO control mechanism enable
software flow control implementation
IrDA mode supports infrared communication
Supports RS-485/9-bit/EIA-485 mode
Built-in fractional baud-rate generator eliminates need for external
crystals of particular values
Supports synchronous mode
16-byte receive and transmit FIFOs
Register locations conform to 16C550 standard
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
Full modem interface
Smart-card (USART) interface selection guide
Series
ARM core
Memory
Smart-card
interface
USART
Flash (KB)
SRAM (KB)
LPC1700
Cortex-M3
Up to 512
Up to 96
1
LPC1800
Cortex-M3
Up to 1024
(2 x 512)
Up to 200
Up to 1
Up to 3
LPC4300
Cortex-M4
Up to 1024
(2 x 512)
Up to 264
Up to 1
Up to 3
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