参数资料
型号: LPC2101FBD48,151
厂商: NXP Semiconductors
文件页数: 37/37页
文件大小: 0K
描述: IC ARM7 MCU FLASH 8K 48-LQFP
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
ARM7 Architecture
ARM7 Memory
标准包装: 250
系列: LPC2100
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 70MHz
连通性: I²C,Microwire,SPI,SSI,SSP,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-LQFP
包装: 托盘
产品目录页面: 704 (CN2011-ZH PDF)
配用: 568-4310-ND - EVAL BOARD LPC2158 W/LCD
568-4297-ND - BOARD EVAL LPC21XX MCB2100
MCB2103UME-ND - BOARD EVAL MCB2103 + ULINK-ME
MCB2103U-ND - BOARD EVAL MCB2103 + ULINK2
622-1005-ND - USB IN-CIRCUIT PROG ARM7 LPC2K
其它名称: 568-2092
935280963151
LPC2101FBD48-S
LPC2101_02_03_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 2 June 2009
9 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
[1]
5 V tolerant (if VDD(3V3) and VDDA ≥ 3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
[2]
Open-drain 5 V tolerant (if VDD(3V3) and VDDA ≥ 3.0 V) digital I/O I2C-bus 400 kHz specication compatible pad. It requires external
pull-up to provide an output functionality. Open-drain conguration applies to ALL functions on that pin.
[3]
5 V tolerant (if VDD(3V3) and VDDA ≥ 3.0 V) pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and
analog input function. If congured for an input function, this pad utilizes built-in glitch lter that blocks pulses shorter than 3 ns. When
congured as an ADC input, digital section of the pad is disabled.
[4]
5 V tolerant (if VDD(3V3) and VDDA ≥ 3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
If congured for an input function, this pad utilizes built-in glitch lter that blocks pulses shorter than 3 ns.
[5]
A LOW level during reset on pin P0.14 is considered as an external hardware request to start the ISP command handler.
[6]
Open-drain 5 V tolerant (if VDD(3V3) and VDDA ≥ 3.0 V) digital I/O I2C-bus 400 kHz specication compatible pad. It requires external
pull-up to provide an output functionality. Open-drain conguration applies only to I2C function on that pin.
[7]
Pad provides special analog functionality.
[8]
For lowest power consumption, pin should be left oating when the RTC is not used.
[9]
See
LPC2101/02/03 User manual UM10161 for details.
VSS
7, 19, 43
I
Ground: 0 V reference.
VSSA
31
I
Analog ground: 0 V reference. This should be nominally the same voltage as
VSS but should be isolated to minimize noise and error.
VDDA
42
I
Analog 3.3 V power supply: This should be nominally the same voltage as
VDD(3V3) but should be isolated to minimize noise and error. The level on this
pin also provides a voltage reference level for the ADC.
VDD(1V8)
5I
1.8 V core power supply: This is the power supply voltage for internal
circuitry and the on-chip PLL.
VDD(3V3)
17, 40
I
3.3 V pad power supply: This is the power supply voltage for the I/O ports.
VBAT
4
I
RTC power supply: 3.3 V on this pin supplies the power to the RTC.
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
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