参数资料
型号: LPC2106FBD48,151
厂商: NXP Semiconductors
文件页数: 9/41页
文件大小: 0K
描述: IC ARM7 MCU FLASH 128K 48-LQFP
标准包装: 250
系列: LPC2100
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 60MHz
连通性: I²C,Microwire,SPI,SSI,SSP,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 128KB(128K x 8)
程序存储器类型: 闪存
RAM 容量: 64K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 3.6 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-LQFP
包装: 托盘
配用: 622-1019-ND - BOARD FOR LPC2106 48-LQFP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
568-1756-ND - BOARD EVAL FOR LPC210X ARM MCU
其它名称: 568-1890
935275298151
LPC2106FBD48-S
LPC2104_2105_2106_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 20 June 2008
17 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Standard modem interface signals included on UART 1.
6.10.2 UART features available in LPC2104/2105/2106/01 only
Compared to previous LPC2000 microcontrollers, UARTs in LPC2104/2105/2106/01
introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers
to achieve standard baud rates such as 115200 Bd with any crystal frequency above
2 MHz. In addition, auto-CTS/RTS ow-control functions are fully implemented in
hardware.
Fractional baud rate generator enables standard baud rates such as 115200 Bd to be
achieved with any crystal frequency above 2 MHz.
Autobauding.
Auto-CTS/RTS ow-control fully implemented in hardware.
6.11 I2C-bus serial I/O controller
I2C is a bidirectional bus for inter-IC control using only two wires: a serial clock line (SCL),
and a serial data line (SDA). Each device is recognized by a unique address and can
operate as either a receiver-only device (e.g. an LCD driver or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. I2C is a multi-master bus, it can be
controlled by more than one bus master connected to it.
The I2C-bus implemented in LPC2104/2105/2106 supports bit rate up to 400 kbit/s (Fast
I2C-bus).
6.11.1 Features
Standard I2C compliant bus interface.
Easy to congure as Master, Slave or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I2C-bus may be used for test and diagnostic purposes.
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