参数资料
型号: LT1240-7DZFB1
厂商: POWER-ONE INC
元件分类: 电源模块
英文描述: 1-OUTPUT 500 W AC-DC REG PWR SUPPLY MODULE
封装: CASE T01, MODULE
文件页数: 33/33页
文件大小: 864K
代理商: LT1240-7DZFB1
Cassette Style
AC-DC Converters
T Series
Edition 5/5.2000
9/33
Uo
Uo min u
Ut
mains failure
warning time
thold
t
U
low load
heavy load
05049
Fig. 10
Hold up and warning time with power down output signal.
The table:
Hold up time also gives information about the
warning time of the power down signal. If for example the
threshold level
Ut of the power down signal is set to 43 V
and the minimum acceptable voltage of the load is 38 V the
time between the activation of the power down signal and
the switch-off of the load (550 W) will be 15 ms (55 ms -
40 ms).
Pulse Loading (Rectifier Version)
To prevent an overload of the output and filter capacitors
the superimposed AC ripple current at the output should be
limited as shown below. For high current pulse loads exter-
nal capacitors are recommended.
For other pulse loads than stated in the figure below, e.g.
Ui
< U
i nom, Io
> I
o nom, please contact Power-One.
15
10
5
0
100
1 k
10 k
Io PL [Arms]
fPL [Hz]
TC = 50°C
TC = TC max
Ui = Ui nom
Average output current = Io nom
Sinusoidal
ripple
current
50
05050
Fig. 11
Maximum allowable AC ripple output current superim-
posed on the average output current Io nom with LT 1701
unit.
Fig. 12
Dynamic characteristics under varying load conditions
(see: Electrical Output Data)
Uo
t d
DUo I
10%
DUo d
t
Io /Io nom
1
0.9
0.1
DUod
05051
Uo
Table 6: Characteristics of the inhibit signal
Characteristics
Conditions
min
typ max
Unit
Uinh Inhibit
Uo = on
Ui min...Ui max
2.5
60
V
voltage
TC min...TC max
Rinh Resistance Uo = on
30
k
to Vo–
Uinh Inhibit
Uo = off
-0.7
0.4
V
voltage
Rinh Resistance Uo = off
50
tr
Switch-on time
Ui nom
100
ms
until full power avail.
Pinh Input power with
3
W
inhibited unit
Fig. 13
Inhibit signal connection
Inhibit input (Rectifier Version)
The rectifier versions are equipped with the inhibit function
only. (The Ucr remote control is used with the battery char-
ger version.)
The unit is enabled by a logic high signal and disabled by a
logic low signal. This input is TTL/CMOS compatible, a re-
sistor
<50 disables the unit, a resistor >30 k enables it.
The switch-on time
tr of the unit, i.e. the time delay between
powering until the full output power is available, is typically
100 ms.
The hold up time at the output after inhibiting depends on
the load, the internal capacitance of the unit and additional
capacitance on the DC bus.
The inhibit input is protected against DC overvoltage up to
60 V.
P~
N~
Vo–
i/Ucr
Vo+
Iinh
Uinh
06116
4
28
12
22
6
T1000
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