参数资料
型号: LT1249CS8#TRPBF
厂商: Linear Technology
文件页数: 7/12页
文件大小: 197K
描述: IC PFC CTRLR AVERAGE CURR 8SOIC
标准包装: 2,500
模式: 平均电流
频率 - 开关: 100kHz
电流 - 启动: 250µA
电源电压: 15.5 V ~ 27 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
LT1249
7
APPLICATIONS INFORMATION
U
U
Line Current Limiting
Maximum voltage across R
MOUT
 is internally limited to
1.1V. Therefore, line current limit is 1.1V divided by the
sense resistor R
S
. With a 0.2& sense resistor R
S
 line
current limit is 5.5A. As a general rule, R
S
 is chosen
according
R
I
R
V
K
P
S
M MAX
MOUT    LINE MIN
OUT MAX
=
(
)(
)(
)
( .    )
(
)
(    )
(
)
1 414
where P
OUT(MAX)
 is the maximum power output and K is
usually between 1.1 and 1.3 depending on efficiency and
resistor tolerance. When the output is overloaded and line
current reaches limit, output voltage V
OUT
 will drop to keep
line current constant. System stability is still maintained
by the current loop which is controlled by the current
amplifier. Further load current increase results in further
V
OUT
 drop and clipping of the line current, which degrades
power factor.
Synchronization
The LT1249 can be externally synchronized in a frequency
range of 127kHz to 160kHz. Figure 2 shows the synchro-
nizing circuit. Synchronizing occurs when CA
OUT
 pin is
pulled below 0.5V with an external transistor and a Schottky
diode. The Schottky diode and the 10k pull-up resistor are
necessary for the required fast slewing back up to the
normal operating voltage on CA
OUT
 after the transistor is
turned off. Positive slewing on CA
OUT
 should be faster
than the oscillator ramp rate of 0.5V/祍.
The width of the synchronizing pulse should be under
60ns. The synchronizing pulses introduce an offset volt-
age on the current amplifier inputs, according to:
V
ts  fs  I
V
R
g
OS
C
C
m
=
+

?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
(  )(  )
.
0 5
2
ts = pulse width
fs = pulse frequency
I
C
 = CA
OUT
 source current (H 150礎)
V
C
 = CA
OUT
 operating voltage (1.8V to 6.8V)
R2 = resistor for the midfrequency zero in the current loop
g
m
 = current amplifier transconductance (H 320祄ho)
With ts = 30ns, fs = 130kHz, V
C
 = 3V and R2 = 10k, offset
voltage shift is H5mV. Note that this offset voltage will add
slight distortion to line current at light load.
Figure 2. Synchronizing the LT1249
R1
10k
R2
10k
2k
5V
0V
V
CC
80pF
1N5712
CA
OUT
1nF
2N2369
1249 F02
Overvoltage Protection
In Figure 3, R1 and R2 set the regulator output DC level:
V
OUT
 = V
REF
[(R1 + R2)/R2]. With R1 = 1M and R2 = 20k,
V
OUT
 is 382V.
Because of the slow loop response necessary for power
factor correction, output overshoot can occur with sudden
load removal or reduction. To protect the power compo-
nents and output load, the LT1249 voltage error amplifier
senses the output voltage and quickly shuts off the current
switch when overvoltage occurs. When overshoot occurs
on V
OUT
, the overcurrent from R1 will go through VA
OUT
because amplifier feedback keeps V
SENSE
 locked at 7.5V.
When this overcurrent reaches 44礎 amplifier sinking
limit, the amplifier loses feedback and its output snaps low
to turn the multiplier off.
Overvoltage trip level: V
OUT
 = (44礎)(R1)

+
V
OUT
VA
OUT
C1
0.47礔
R3
330k
0.047礔
LT1249
MULTIPLIER
44礎
22礎
V
SENSE
R1
1M
R2
20k
V
REF
7.5V
EA
1249 F03
Figure 3. Overvoltage Protection
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