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| 型号： | LT1306ES8#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 7/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BOOST 5V 1A 8SOIC |
| 标准包装： | 100 |
| 类型： | 升压（升压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 5V |
| 输入电压： | 1.8 V ~ 7 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 310kHz |
| 电流 - 输出： | 1A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
| 供应商设备封装： | 8-SOIC |
LT1306
OPERATIO
The LT1306 is a fixed frequency current mode PWM
regulator with integrated power transistor Q1 and syn-
chronous rectifier Q2.
In the Block Diagram, Figure 2, the PWM control circuit
is enclosed within the dashed line. It consists of the
current sense amplifier (A2), the oscillator, the compen-
sating ramp generator, the PWM comparator (A4), the
logic (X1 and X2), the power transistor driver (X4) and
the main power switch (Q1). Notice that the clock (CLK)
“blanks” Q1 conduction. The internal oscillator frequency
is 300kHz.
The pulse width of the clock determines the maximum on
duty ratio of Q1. In the LT1306 this is set to 88%. Q1 turns
on at the trailing edge of the clock pulse. To prevent
subharmonic oscillation above 50% duty ratio, a com-
pensating ramp (generated from the oscillator sawtooth)
is added to the sensed Q1 current. Q1 is turned off when
this sum exceeds the error amplifier A1 output, V C . Q1’s
absolute current limit is reached when V C ’s upward
excursion is clamped internally at 1.28V.
The error amplifier output, V C , determines the peak switch
current required to regulate the output voltage. V C is a
measure of the output power. At heavy loads, the average
and the peak inductor currents are both high. V C moves to
the upper end of its operating range and the LT1306 oper-
ates in continuous conduction mode (CCM).
As load decreases, the average inductor current de-
creases. In CCM, the peak-to-peak inductor current ripple
to the first order depends only on the inductance, the
input and the output voltages. When the average inductor
current falls below 1/2 of the peak-to-peak inductor
current ripple, the converter enters discontinuous con-
duction mode (DCM). The switching frequency remains
constant except that the inductor current always returns
to zero within each switching cycle.
In both CCM and DCM, the output voltage is regulated
with negative feedback. A1 amplifies the error voltage
between the internally generated 1.24V reference and the
attenuated output voltage. The RC network from the V C
pin to ground provides the loop compensation.
Further reduction in the load moves V C towards the lower
and switch Q1’s on-time decrease. Hysteretic comparator
A3 determines if V C is too low for the LT1306 to operate
efficiently. As V C falls below the trip voltage V B , the output
of A3 goes high. All circuits except the error amplifier,
comparators A3 and A5, and the rectifier driver control X5,
are turned off. After the remaining energy stored in the
inductor is delivered to the output through the synchro-
nous rectifier Q2, the LT1306 stops switching. In this idle
state, the LT1306 draws only 160 μ A from the input. With
switching stopped and the load being powered by the
output filter capacitor, the output voltage decreases. V C
then starts to increase. Q1 does not start to switch until V C
rises above the upper trip point of A3. The LT1306 again
delivers power to the output as a current mode PWM
converter except that the switch current limit is only about
250mA due to the low value of V C . If the load is still light,
the output voltage will rise and V C will fall, causing the
converter to idle again. Power delivery therefore occurs in
bursts. The on-off cycle frequency, or burst frequency,
depends on the operating conditions, the inductance and
the output filter capacitance. The output voltage ripple in
Burst Mode operation is usually higher than either CCM or
DCM operation. Burst Mode operation increases light load
efficiency because it delivers more energy to the output
during each clock cycle than is possible with DCM
operation’s extremely low peak switch current. This al-
lows fewer switching cycles per unit time to maintain a
given output. Chip supply current therefore becomes a
small fraction of the total input current.
The synchronous rectifier is represented as NPN transis-
tor, Q2, in the Block Diagram (Figure 2). A rectifier drive
circuit, X5, supplies variable base drive to Q2 and controls
the voltage across the rectifier. The supply voltage, V CAP ,
for the driver is generated locally with the bootstrap cir-
cuit, D1 and C1 (Figure 1). When Q1 is on, the bootstrap
capacitor C1 is charged from the input to the voltage
V IN – V D1(ON) – V CESAT1 . The charging current flows from
the input through D1, C1 and Q1 to ground. After Q1 is
switched off, the node SW goes above V O by the rectifier
drop V CESAT2 . D1 becomes back-biased and the CAP volt-
age is pushed up to V O + V CESAT2 + V IN – V D1(ON) – V CESAT1 .
C1 supplies the base drive to Q2. The consumed charge is
replenished during the Q1 on interval.
end of its operating range. Both the peak inductor current
7
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