参数资料
型号: LT1371CT7
厂商: Linear Technology
文件页数: 11/16页
文件大小: 0K
描述: IC REG MULTI CONFIG ADJ TO220-7
标准包装: 50
类型: 降压(降压),升压(升压),反相,Cuk,回扫,正向转换器
输出类型: 可调式
输出数: 1
输出电压: 1.25 V ~ 35 V
输入电压: 2.7 V ~ 25 V
PWM 型: 电流模式
频率 - 开关: 500kHz
电流 - 输出: 3A
同步整流器:
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: TO-220-7 成形引线
包装: 管件
供应商设备封装: TO-220-7
LT1371
APPLICATIO S I FOR ATIO
maximum output load current and will also be increased if
poor quality (high ESR) output capacitors are used. The
addition of a 0.0047 μ F capacitor on the V C pin reduces
switching frequency ripple to only a few millivolts. A low
value for R C will also reduce V C pin ripple, but loop phase
margin may be inadequate.
Layout Considerations
For maximum efficiency, LT1371 switch rise and fall times
are made as short as possible. To prevent radiation and
high frequency resonance problems, proper layout of the
components connected to the switch node is essential. B
field (magnetic) radiation is minimized by keeping output
diode, Switch pin and output bypass capacitor leads as
CONNECT
GROUND PIN
AND TAB DIRECTLY
TO GROUND PLANE.
TAB MAY BE
SOLDERED OR
BOLTED TO
GROUND PLANE*
V C
FB
GND S/S
NFB V SW
V IN
D
C
C
KEEP PATH FROM
V SW , OUTPUT DIODE,
OUTPUT CAPACITORS
AND GROUND RETURN
AS SHORT AS POSSIBLE
short as possible. Figures 3, 4 and 5 show recommended
positions for these components. E field radiation is kept
low by minimizing the length and area of all traces con-
nected to the Switch pin. A ground plane should always be
used under the switcher circuitry to prevent interplane
coupling.
*SEE T7 PACKAGE LAYOUT CONSIDERATIONS FOR VERTICAL MOUNTING
OF THE T7 PACKAGE
Figure 4. Layout Considerations — T7 Package
LT1371 ? F04
The high speed switching current path is shown schemati-
cally in Figure 6. Minimum lead length in this path is
essential to ensure clean switching and low EMI. The path
including the switch, output diode and output capacitor is
the only one containing nanosecond rise and fall times.
Keep this path as short as possible.
V C
FB
NFB
GND
GND
GND
V SW
NC
V SW
GND
GND
GND
D
C
C
KEEP PATH FROM
V SW , OUTPUT DIODE,
OUTPUT CAPACITORS
AND GROUND RETURN
AS SHORT AS POSSIBLE
GND
SHDN
SYNC
V IN
GND
NC
NC
GND
CONNECT ALL GROUND PINS TO GROUND PLANE
LT1371 ? F05
FB
GND
S/S
CONNECT
V C
NFB
V SW
V IN
C
C
Figure 5. Layout Considerations — SW Package
GROUND PIN
AND TAB DIRECTLY
TO GROUND PLANE
D
KEEP PATH FROM
V SW , OUTPUT DIODE,
OUTPUT CAPACITORS
AND GROUND RETURN
L1
SWITCH
NODE
HIGH
V OUT
AS SHORT AS POSSIBLE
LT1371 ? F03
V IN
FREQUENCY
CIRCULATING
LOAD
PATH
Figure 3. Layout Considerations — R Package
LT1371 ? F06
Figure 6
11
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