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| 型号： | LT1424CN8-9#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC REG FLYBACK ISOLATED 9V 8DIP |
| 标准包装： | 50 |
| 类型： | 回扫，隔离 |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 9V |
| 输入电压： | 2.8 V ~ 20 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 285kHz |
| 电流 - 输出： | 200mA |
| 同步整流器： | 无 |
| 工作温度： | 0°C ~ 125°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 包装： | 管件 |
| 供应商设备封装： | 8-PDIP |
LT1424-9
APPLICATIO N S I N FOR M ATIO N
) ) ) )
[V OUT ? (t EN + t ED )] 2
Min Power =
) ) ) )
(t ED + t EN ) 2 , where
L SEC
I OUT(MIN) =
) )
I IN = 7mA + DC where,
MINIMUM LOAD CONSIDERATIONS
The LT1424-9 generally provides better low load perfor-
mance than previous generation switcher/controllers
utilizing indirect output voltage sensing techniques. Spe-
cifically, it contains circuitry to detect flyback pulse
“collapse,” thereby supporting operation well into dis-
continuous mode. In general, there are two possible
constraints to ultimate low load operation, minimum
switch ON time which sets a minimum level of delivered
power, and minimum flyback enable time, which deals
with the ability of the feedback system to derive valid
output voltage information from the flyback pulse. In the
application for which the LT1424-9 is designed, the
minimum flyback enable time is more restrictive.
The LT1424-9 derives its output voltage information from
the flyback pulse. If the internal minimum enable time
pulse extends beyond the flyback pulse, loss of regulation
will occur. The onset of this condition can be determined
by setting the width of the flyback pulse equal to the sum
of the flyback enable delay, t ED , plus the minimum enable
time, t EN . Minimum power delivered to the load is then:
1 f
2 L SEC
= (V OUT )(I OUT )
Which yields a minimum output constraint:
1 f(V OUT )
2
f = Switching frequency (nominally 285kHz)
L SEC = Transformer secondary side inductance
V OUT = Output voltage
t ED = Enable delay time
t EN = Minimum enable time
In reality, the previously derived expression is a conserva-
tive one, as it assumes perfectly “square” waveforms,
which is not the case at light load. Furthermore, the
equation was set up to yield just the onset of control error.
In other words, while the equation suggests a minimum
suggest operation down to 2mA to 3mA before significant
output voltage rise is observed. Nevertheless, this situa-
tion is addressed in the application by the use of a fixed
1.8k load resistor, which preloads the supply with a
nominal 5mA.
MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS
The LT1424-9 is a current mode controller. It uses the V C
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the V C
node, nominally 1.9V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
then determined by the switch current limit, which is
somewhat duty cycle dependent due to internal slope
compensation action.
Short-circuit conditions are handled by the same mecha-
nism. The output switch turns on, peak current is quickly
reached and the switch is turned off. Because the output
switch is only on for a small fraction of the available period,
internal power dissipation is controlled. (The LT1424-9
contains an internal overtemperature shutdown circuit,
that disables switch action, just in case.)
THERMAL CONSIDERATIONS
Care should be taken to ensure that the worst-case input
voltage and load current conditions do not cause exces-
sive die temperatures. The packages are rated at 110 ° C/W
for SO-8 and 130 ° C/W for N8.
Average supply current (including driver current) is:
I SW
35
I SW = Switch current
DC = On switch duty cycle
Switch power dissipation is given by:
P SW = (I SW ) 2 (R SW )(DC)
R SW = Output switch ON resistance
load current of perhaps 7mA, laboratory observations
sn14249 14249fs
12
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