参数资料
型号: LT1529IT#PBF
厂商: Linear Technology
文件页数: 7/12页
文件大小: 0K
描述: IC REG LDO ADJ 3A TO220-5
产品培训模块: More Information on LDOs
标准包装: 50
稳压器拓扑结构: 正,可调式
输出电压: 3.3 V ~ 14.15 V
输入电压: 3.8 V ~ 15 V
电压 - 压降(标准): 0.6V @ 3A
稳压器数量: 1
电流 - 输出: 3A
电流 - 限制(最小): 3.2A
工作温度: -45°C ~ 125°C
安装类型: 通孔
封装/外壳: TO-220-5 成形引线
供应商设备封装: TO-220-5
包装: 管件
LT1529
LT1529-3.3/LT1529-5
TYPICAL PERFOR A CE C HARA C TERISTICS
Load Regulation
LT1529-5 Transient Response
LT1529-5 Transient Response
5
0
–5
LT1529-5
LT1529-3.3
LT1529
0.2
0.1
0
– 0.1
V IN = 6V
C IN = 3.3 μ F
C OUT = 47 μ F
0.2
0.1
0
– 0.1
V IN = 6V
C IN = 10 μ F
C OUT = 22 μ F
–10
–15
– 0.2
3
– 0.2
3
–20
V IN = V OUT (NOMINAL) + 1V
? I LOAD = 100mA to 3A
V ADJ = V OUT
2
1
2
1
–25
– 50 – 25
0
25 50 75
100
125
0 100 200 300 400 500 600 700 800 900 1000
0
20 40 60 80 100 120 140 160 180 200
TEMPERATURE ( ° C)
PI FU CTIO S
LT1529 ? G28
TIME ( μ s)
LT1529 ? G29
TIME ( μ s)
LT1529 ? G30
OUTPUT (Pin 1): OUTPUT Pin. The OUTPUT pin supplies
power to the load. A minimum output capacitor of 22 μ F is
5
V IN OUTPUT
LT1529-5
1
R P
required to prevent oscillations. Larger values will be
required to optimize transient response for large load
V IN
+
4
SHDN SENSE
GND
2
+
LOAD
current deltas. See the Applications Information section
3
for further information on output capacitance and reverse
output characteristics.
R P
LT1529 ? F01
SENSE (Pin 2): SENSE Pin. For fixed voltage versions of
the LT1529 (LT1529-3.3, LT1529-5) the SENSE pin is the
input to the error amplifier. Optimum regulation will be
obtained at the point where the SENSE pin is connected to
the output pin. For most applications the SENSE pin is
connected directly to the OUTPUT pin at the regulator. In
critical applications small voltage drops caused by the
resistance (R P ) of PC traces between the regulator and the
load, which would normally degrade regulation, may be
eliminated by connecting the SENSE pin to the OUTPUT
pin at the load as shown in Figure 1 (Kelvin Sense Connec-
tion). Note that the voltage drop across the external PC
traces will add to the dropout voltage of the regulator. The
SENSE pin bias current is 15 μ A at the nominal regulated
output voltage. This pin is internally clamped to – 0.6V
(one V BE ).
ADJ (Pin 2): Adjust Pin. For the LT1529 (adjustable
version) the ADJ pin is the input to the error amplifier. This
Figure 1. Kelvin Sense Connection
pin is internally clamped to 6V and – 0.6V (one V BE ). This
pin has a bias current of 150nA which flows into the pin.
See Bias Current curve in the Typical Performance Char-
acteristics. The ADJ pin reference voltage is equal to 3.75V
referenced to ground.
SHDN (Pin 4): Shutdown Pin. This pin is used to put the
device into shutdown. In shutdown the output of the
device is turned off. This pin is active low. The device will
be shut down if the SHDN pin is actively pulled low. The
SHDN pin current with the pin pulled to ground will be 6 μ A.
The SHDN pin is internally clamped to 7V and – 0.6V (one
V BE ). This allows the SHDN pin to be driven directly by 5V
logic or by open-collector logic with a pull-up resistor. The
pull-up resistor is only required to supply the leakage
current of the open-collector gate, normally several mi-
croamperes. Pull-up current must be limited to a maxi-
mum of 5mA. A curve of SHDN pin input current as a
152935fb
7
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